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X5648S14I-2.7T1 PDF预览

X5648S14I-2.7T1

更新时间: 2024-01-28 14:23:02
品牌 Logo 应用领域
瑞萨 - RENESAS 可编程只读存储器电动程控只读存储器电可擦编程只读存储器光电二极管内存集成电路
页数 文件大小 规格书
18页 710K
描述
X5648S14I-2.7T1

X5648S14I-2.7T1 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
Reach Compliance Code:not_compliant风险等级:5.85
数据保留时间-最小值:100耐久性:100000 Write/Erase Cycles
JESD-30 代码:R-PDSO-G14JESD-609代码:e0
内存密度:65536 bit内存集成电路类型:EEPROM
内存宽度:8湿度敏感等级:1
端子数量:14字数:8192 words
字数代码:8000最高工作温度:85 °C
最低工作温度:-40 °C组织:8KX8
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP14,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE并行/串行:SERIAL
电源:3/5 V认证状态:Not Qualified
串行总线类型:SPI最大待机电流:0.000001 A
子类别:EEPROMs最大压摆率:0.005 mA
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL写保护:HARDWARE/SOFTWARE
Base Number Matches:1

X5648S14I-2.7T1 数据手册

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DATASHEET  
X5648, X5649 (Replaces X25648, X25649)  
CPU Supervisor with 64Kbit SPI EEPROM  
FN8136  
Rev 0.00  
March 17, 2005  
FEATURES  
DESCRIPTION  
• Low V detection and reset assertion  
—Five standard reset threshold voltages  
These devices combine three popular functions, Power-  
on Reset Control, Supply Voltage Supervision, and Block  
Lock Protect Serial EEPROM Memory in one package.  
This combination lowers system cost, reduces board  
space requirements, and increases reliability.  
CC  
—Re-program low V reset threshold voltage  
CC  
using special programming sequence  
—Reset signal valid to V = 1V  
CC  
• Long battery life with low power consumption  
—<50µA max standby current, watchdog on  
—<1µA max standby current, watchdog off  
—<400µA max active current during read  
• 64Kbits of EEPROM  
Applying power to the device activates the power-on  
reset circuit which holds RESET/RESET active for a  
period of time. This allows the power supply and oscilla-  
tor to stabilize before the processor can execute code.  
• Built-in inadvertent write protection  
—Power-up/power-down protection circuitry  
—Protect 0, 1/4, 1/2 or all of EEPROM array with  
The device’s low V  
user’s system from low voltage conditions by holding  
RESET/RESET active when V falls below a minimum  
detection circuitry protects the  
CC  
CC  
Block Lock protection  
V
V
trip point. RESET/RESET remains asserted until  
returns to proper operating level and stabilizes. Five  
CC  
—In circuit programmable ROM mode  
• 2MHz SPI interface modes (0,0 & 1,1)  
• Minimize EEPROM programming time  
—32-byte page write mode  
CC  
industry standard V  
thresholds are available,  
TRIP  
however, Intersil’s unique circuits allow the threshold to  
be reprogrammed to meet custom requirements or to  
fine-tune the threshold in applications requiring higher  
precision.  
—Self-timed write cycle  
—5ms write cycle time (typical)  
• 2.7V to 5.5V and 4.5V to 5.5V power supply  
operation  
• Available packages  
—14-lead SOIC, 8-lead PDIP  
BLOCK DIAGRAM  
WP  
Protect Logic  
SI  
Data  
Register  
Status  
Register  
SO  
Command  
Decode &  
Control  
SCK  
CS  
16Kbits  
16Kbits  
Logic  
32Kbits  
Reset  
Timebase  
RESET/RESET  
Power-on and  
Low Voltage  
Reset  
V
+
-
CC  
X5648 = RESET  
X5649 = RESET  
Generation  
V
TRIP  
FN8136 Rev 0.00  
March 17, 2005  
Page 1 of 18  

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