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X5328S8ZT1 PDF预览

X5328S8ZT1

更新时间： 2024-09-16 15:58:07
品牌 Logo 应用领域
瑞萨 - RENESAS 可编程只读存储器电动程控只读存储器电可擦编程只读存储器光电二极管
页数 文件大小 规格书
21页 818K
描述
CPU Supervisor with 32Kbit SPI EEPROM; SOIC8; Temp Range: See Datasheet

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中文翻译

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X5328S8ZT1 技术参数

生命周期：Unknown零件包装代码：SOIC
包装说明：SOP,针数：8
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.11
Is Samacsys：N其他特性：WATCHDOG TIMER, POWER-ON RESET CONTROL, SUPPLY VOLTAGE SUPERVISION
可调阈值：YES模拟集成电路 - 其他类型：POWER SUPPLY SUPPORT CIRCUIT
JESD-30 代码：R-PDSO-G8JESD-609代码：e3
长度：4.9 mm湿度敏感等级：1
信道数量：1功能数量：1
端子数量：8最高工作温度：70 °C
最低工作温度：封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：260
认证状态：Not Qualified座面最大高度：1.75 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Matte Tin (Sn) - annealed端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：30宽度：3.9 mm
Base Number Matches：1

X5328S8ZT1 数据手册

 浏览型号X5328S8ZT1的Datasheet PDF文件第2页浏览型号X5328S8ZT1的Datasheet PDF文件第3页浏览型号X5328S8ZT1的Datasheet PDF文件第4页浏览型号X5328S8ZT1的Datasheet PDF文件第5页浏览型号X5328S8ZT1的Datasheet PDF文件第6页浏览型号X5328S8ZT1的Datasheet PDF文件第7页 
DATASHEET  
X5328, X5329 (Replaces X25328, X25329)  
CPU Supervisor with 32Kbit SPI EEPROM  
FN8132  
Rev 2.00  
October 16, 2015  
FEATURES  
DESCRIPTION  
• Low V detection and reset assertion  
—Five standard reset threshold voltages  
These devices combine three popular functions, Power-  
on Reset Control, Supply Voltage Supervision, and Block  
Lock Protect Serial EEPROM Memory in one package.  
This combination lowers system cost, reduces board  
space requirements, and increases reliability.  
CC  
—Re-program low V reset threshold voltage  
CC  
using special programming sequence  
—Reset signal valid to V = 1V  
CC  
• Long battery life with low power consumption  
—<1µA max standby current  
—<400µA max active current during read  
• 32Kbits of EEPROM  
Applying power to the device activates the power-on  
reset circuit which holds RESET/RESET active for a  
period of time. This allows the power supply and oscilla-  
tor to stabilize before the processor can execute code.  
• Built-in inadvertent write protection  
—Power-up/power-down protection circuitry  
—Protect 0, 1/4, 1/2 or all of EEPROM array with  
The device’s low V  
detection circuitry protects the  
CC  
user’s system from low voltage conditions by holding  
RESET/RESET active when V falls below a mini-  
™
Block Lock protection  
CC  
—In circuit programmable ROM mode  
• 2MHz SPI interface modes (0,0 & 1,1)  
• Minimize EEPROM programming time  
—32-byte page write mode  
mum V trip point. RESET/RESET remains asserted  
CC  
until V  
returns to proper operating level and stabi-  
CC  
lizes. Five industry standard V  
thresholds are  
TRIP  
available, however, Intersil’s unique circuits allow the  
threshold to be reprogrammed to meet custom  
requirements or to fine-tune the threshold in applica-  
tions requiring higher precision.  
—Self-timed write cycle  
—5ms write cycle time (typical)  
• 2.7V to 5.5V and 4.5V to 5.5V power supply  
operation  
• Available packages  
—14 Ld TSSOP, 8 Ld SOIC, 8 Ld PDIP  
• Pb-free plus anneal available (RoHS compliant)  
BLOCK DIAGRAM  
WP  
Protect Logic  
SI  
Data  
Status  
Register  
Register  
SO  
Command  
Decode &  
Control  
SCK  
CS  
8Kbits  
8Kbits  
Logic  
16Kbits  
Reset  
Timebase  
RESET/RESET  
Power-on and  
Low Voltage  
Reset  
VCC  
+
-
Generation  
X5328 = RESET  
X5329 = RESET  
VTRIP  
FN8132 Rev 2.00  
October 16, 2015  
Page 1 of 21  
1234567...21

中文翻译

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