Datasheet > X4C105V20I

X4C105V20I

更新时间： 2024-02-11 19:40:12

品牌	Logo	应用领域
英特矽尔 - INTERSIL		光电二极管监控
页数	文件大小	规格书
19页	295K
描述
CPU Supervisor with NOVRAM and Output Ports

阅读下载

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

X4C105V20I 技术参数

生命周期：	Obsolete	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.84
Is Samacsys：	N	Base Number Matches：	1

X4C105V20I 数据手册

X4C105

4K, NOVRAM/EEPROM

Data Sheet

March 18, 2005

FN8124.0

DESCRIPTION

CPU Supervisor with NOVRAM and

Output Ports

The low voltage X4C105 combines several functions

into one device. The first is a 2-wire, 4Kbit serial

EEPROM memory with write protection. A Write Pro-

tect (WP) pin provides hardware protection for the

upper half of this memory against inadvertent writes.

FEATURES

• 4Kbit serial EEPROM

—400kHz serial interface speed

—16-byte page write mode

• One nibble NOVRAM

—120ns NOVRAM access speed

—AUTOSTORE

A one nibble NOVRAM is provided and occupies a sin-

gle location. This allows access of 4-bits in a single

150ns cycle. This is useful for tracking system opera-

tion or process status. The NOVRAM memory is com-

pletely isolated from the serial memory section.

—Direct/bus access of NOVRAM bits

• Four output ports

• Operates at 3.3V ± 10%

A low voltage detect circuit activates a RESET pin

• Low voltage reset when V < 3V

when V

drops below 3V. This signal also blocks

—3% accurate thresholds available

—Output signal shows low voltage condition

—Activates NOVRAM AUTOSTORE

—Internal block on EEPROM operation

• Max EEPROM/NOVRAM nonvolatile write cycle:

5ms

new read or write operations and initiates a NOVRAM

AUTOSTORE. The AUTOSTORE operation is pow-

ered by an external capacitor to ensure that the value

in the NOVRAM is always maintained in the event of a

power failure.

The four NOVRAM bits also appear on four separate

output pins to allow continuous control of external cir-

cuitry, such as ASICs.

• High reliability

—1,000,000 endurance cycles

—Guaranteed data retention: 100 years

• 20-lead TSSOP package

Intersil EEPROMs are designed and tested for appli-

cations requiring extended endurance. Inherent data

retention is greater than 100 years.

BLOCK DIAGRAM

Write Control Logic

HV Generation

EEPROM

Memory

Output

Buffers

and

Timing and Control

Latches

Static RAM

Memory

4Kbits

SCL

SDA

Command

Decode

and

EEPROM

Array

I/O

Buffers

Control

Logic

Control

Logic

and

Y Decoder

Data Register

Timing

CAP

V_CC

V_SS

Low Voltage Detect

Power-on Reset

Voltage

Monitor

Supply

RESET

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

12 3 4 5 6 7...19

下载PDF

与X4C105V20I相关器件

型号	品牌	描述	获取价格	数据表
X4C105V20I-VTRIP	ETC	EEPROM	获取价格
X4C105V20-VTRIP	ETC	EEPROM	获取价格
X4C20F1-30S	ANAREN	RF Couplers Dual-directional Coupling 30dB 1GHz to 3GHz 5-Pin T/R	获取价格
X4C20J1-02G	ANAREN	Directional Coupler 5G 2DB 0805	获取价格
X4C20J1-03G	ANAREN	Ultra Low Profile 08053dB Hybrid Coupler	获取价格
X4C20J1-04G	ANAREN	Directional Coupler 5G 4DB 0805	获取价格