Datasheet > X4C105V20-VTRIP

X4C105V20-VTRIP

更新时间： 2024-02-20 18:21:45

品牌	Logo	应用领域
其他 - ETC		可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数	文件大小	规格书
19页	260K
描述
EEPROM

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技术参数
数据手册

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X4C105V20-VTRIP 技术参数

生命周期：	Obsolete	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.84
Is Samacsys：	N	Base Number Matches：	1

X4C105V20-VTRIP 数据手册

NOVRAM/EEPROM

X4C105

CPU Supervisor with NOVRAM and Output Ports

DESCRIPTION

FEATURES

The low voltage X4C105 combines several functions

into one device. The ﬁrst is a 2-wire, 4Kbit serial

EEPROM memory with write protection. A Write Pro-

tect (WP) pin provides hardware protection for the

upper half of this memory against inadvertent writes.

• 4Kbit serial EEPROM

—400kHz serial interface speed

—16-byte page write mode

• One nibble NOVRAM

—120ns NOVRAM access speed

—AUTOSTORE

—Direct/bus access of NOVRAM bits

• Four output ports

• Operates at 3.3V 10ꢀ

A one nibble NOVRAM is provided and occupies a sin-

gle location. This allows access of 4-bits in a single

150ns cycle. This is useful for tracking system opera-

tion or process status. The NOVRAM memory is com-

pletely isolated from the serial memory section.

• Low voltage reset when V

< 3V

—3ꢀ accurate thresholds available

—Output signal shows low voltage condition

—Activates NOVRAM AUTOSTORE

—Internal block on EEPROM operation

• Max EEPROM/NOVRAM nonvolatile write cycle:

5ms

A low voltage detect circuit activates a RESET pin

when V

drops below 3V. This signal also blocks new

read or write operations and initiates a NOVRAM

AUTOSTORE. The AUTOSTORE operation is pow-

ered by an external capacitor to ensure that the value

in the NOVRAM is always maintained in the event of a

power failure.

• High reliability

—1,000,000 endurance cycles

—Guaranteed data retention: 100 years

• 20-lead TSSOP package

The four NOVRAM bits also appear on four separate

output pins to allow continuous control of external cir-

cuitry, such as ASICs.

Xicor EEPROMs are designed and tested for applica-

tions requiring extended endurance. Inherent data

retention is greater than 100 years.

BLOCK DIAGRAM

Write Control Logic

HV Generation

EEPROM

Memory

Output

Buffers

and

Timing and Control

Latches

Static RAM

Memory

4Kbits

SCL

SDA

Command

Decode

and

EEPROM

Array

I/O

Buffers

Control

Logic

Control

Logic

and

Y Decoder

Data Register

Timing

CAP

Low Voltage Detect

Power On Reset

Voltage

Monitor

Supply

RESET

Characteristics subject to change without notice. 1 of 19

REV 1.0.1 6/14/01

www.xicor.com

12 3 4 5 6 7...19

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