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X4323V8IZ

更新时间: 2024-01-08 18:52:22
品牌 Logo 应用领域
英特矽尔 - INTERSIL 监控可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
22页 343K
描述
CPU Supervisor with 32k EEPROM

X4323V8IZ 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSSOP,
针数:8Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.69Is Samacsys:N
其他特性:RESET THRESHOLD VOLTAGE IS 4.38V可调阈值:YES
模拟集成电路 - 其他类型:POWER SUPPLY MANAGEMENT CIRCUITJESD-30 代码:R-PDSO-G8
JESD-609代码:e3长度:4.4 mm
湿度敏感等级:3信道数量:1
功能数量:1端子数量:8
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260认证状态:Not Qualified
座面最大高度:1.2 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:MATTE TIN
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
宽度:3 mmBase Number Matches:1

X4323V8IZ 数据手册

 浏览型号X4323V8IZ的Datasheet PDF文件第2页浏览型号X4323V8IZ的Datasheet PDF文件第3页浏览型号X4323V8IZ的Datasheet PDF文件第4页浏览型号X4323V8IZ的Datasheet PDF文件第6页浏览型号X4323V8IZ的Datasheet PDF文件第7页浏览型号X4323V8IZ的Datasheet PDF文件第8页 
X4323, X4325  
PRINCIPLES OF OPERATION  
Power-on Reset  
LOW periodically, while SCL is HIGH (this is a start bit)  
prior to the expiration of the watchdog time out period to  
prevent a RESET/RESET signal. The state of two non-  
volatile control bits in the Status Register determine  
the watchdog timer period. The microprocessor can  
change these watchdog bits, or they may be “locked”  
by tying the WP pin HIGH.  
Application of power to the X4323, X4325 activates a  
Power-on Reset Circuit that pulls the RESET/RESET  
pin active. This signal provides several benefits.  
– It prevents the system microprocessor from starting  
to operate with insufficient voltage.  
EEPROM INADVERTENT WRITE PROTECTION  
– It prevents the processor from operating prior to sta-  
bilization of the oscillator.  
When RESET/RESET goes active as a result of a low  
voltage condition or Watchdog Timer Time Out, any in-  
progress communications are terminated. While  
RESET/RESET is active, no new communications are  
allowed and no nonvolatile write operation can start.  
Nonvolatile writes in-progress when RESET/RESET  
goes active are allowed to finish.  
– It allows time for an FPGA to download its configura-  
tion prior to initialization of the circuit.  
– It prevents communication to the EEPROM, greatly  
reducing the likelihood of data corruption on power-up.  
When V  
exceeds the device V  
threshold value  
CC  
TRIP  
Additional protection mechanisms are provided with  
memory Block Lock and the Write Protect (WP) pin.  
These are discussed elsewhere in this document.  
for  
200ms  
(nominal)  
the  
circuit  
releases  
RESET/RESET allowing the system to begin operation.  
LOW VOLTAGE MONITORING  
V
THRESHOLD RESET PROCEDURE  
CC  
During operation, the X4323, X4325 monitors the V  
CC  
The X4323, X4325 is shipped with a standard V  
level and asserts RESET/RESET if supply voltage  
falls below preset minimum The  
CC  
threshold (V  
) voltage. This value will not change  
a
V
.
TRIP  
TRIP  
over normal operating and storage conditions. How-  
ever, in applications where the standard V is not  
RESET/RESET signal prevents the microprocessor  
from operating in a power fail or brownout condition.  
The RESET/RESET signal remains active until the  
voltage drops below 1V. It also remains active until  
TRIP  
exactly right, or if higher precision is needed in the  
value, the X4323, X4325 threshold may be  
V
TRIP  
adjusted. The procedure is described in the following  
section, and uses the application of a nonvolatile con-  
trol signal.  
V
returns and exceeds V  
for 200ms.  
CC  
TRIP  
WATCHDOG TIMER  
The Watchdog Timer circuit monitors the microproces-  
sor activity by monitoring the SDA and SCL pins. The  
microprocessor must toggle the SDA pin HIGH to  
Figure 1. Set V  
Level Sequence (V = desired V values WEL bit set)  
TRIP  
TRIP  
CC  
VP = 12-15V  
WP  
0 1 2 3 4 5 6 7  
0 1 2 3 4 5 6 7  
0 1 2 3 4 5 6 7  
0 1 2 3 4 5 6 7  
SCL  
SDA  
A0h  
00h  
01h  
00h  
FN8122.1  
May 25, 2006  
5

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