Datasheet > X4323

X4323

更新时间： 2022-11-25 17:28:52

品牌	Logo	应用领域
英特矽尔 - INTERSIL		监控可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数	文件大小	规格书
21页	331K
描述
CPU Supervisor with 32K EEPROM

阅读下载

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

X4323 数据手册

X4323, X4325

Serial Start Condition

Serial Stop Condition

All commands are preceded by the start condition,

which is a HIGH to LOW transition of SDA when SCL

is HIGH. The device continuously monitors the SDA

and SCL lines for the start condition and will not

respond to any command until this condition has been

met. See Figure 6.

All communications must be terminated by a stop con-

dition, which is a LOW to HIGH transition of SDA when

SCL is HIGH. The stop condition is also used to place

the device into the Standby power mode after a read

sequence. A stop condition can only be issued after the

transmitting device has released the bus. See Figure 6.

Figure 6. Valid Start and Stop Conditions

SCL

SDA

Start

Stop

Serial Acknowledge

will acknowledge all incoming data and address bytes,

except for the Slave Address Byte when the Device

Identifier and/or Select bits are incorrect.

Acknowledge is a software convention used to indi-

cate successful data transfer. The transmitting device,

either master or slave, will release the bus after trans-

mitting eight bits. During the ninth clock cycle, the

receiver will pull the SDA line LOW to acknowledge

that it received the eight bits of data. Refer to Figure 7.

In the read mode, the device will transmit eight bits of

data, release the SDA line, then monitor the line for an

acknowledge. If an acknowledge is detected and no

stop condition is generated by the master, the device

will continue to transmit data. The device will terminate

further data transmissions if an acknowledge is not

detected. The master must then issue a stop condition

to return the device to Standby mode and place the

device into a known state.

The device will respond with an acknowledge after

recognition of a start condition and if the correct

Device Identifier and Select bits are contained in the

Slave Address Byte. If a write operation is selected,

the device will respond with an acknowledge after the

receipt of each subsequent eight bit word. The device

Figure 7. Acknowledge Response From Receiver

SCL from

Master

Data Output

from

Data Output

from Receiver

Start

Acknowledge

FN8122.0

March 29, 2005

1...5 6 789 10 11...21

下载PDF

与X4323相关器件

型号	品牌	描述	获取价格	数据表
X4323_06	INTERSIL	CPU Supervisor with 32k EEPROM	获取价格
X4323S8	INTERSIL	CPU Supervisor with 32K EEPROM	获取价格
X4323S8-2.7	INTERSIL	CPU Supervisor with 32K EEPROM	获取价格
X4323S8-2.7A	INTERSIL	CPU Supervisor with 32K EEPROM	获取价格
X4323S8-2.7A	XICOR	Power Supply Management Circuit, Adjustable, 1 Channel, CMOS, PDSO8, PLASTIC, SOIC-8	获取价格
X4323S8-4.5A	INTERSIL	CPU Supervisor with 32K EEPROM	获取价格