Datasheet > X4323

X4323

更新时间： 2022-11-25 17:28:52

品牌	Logo	应用领域
英特矽尔 - INTERSIL		监控可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数	文件大小	规格书
21页	331K
描述
CPU Supervisor with 32K EEPROM

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X4323 数据手册

X4323, X4325

Writing to the Control Register

– The RWEL bit cannot be reset without writing to the

nonvolatile control bits in the control register, power

cycling the device or attempting a write to a write

protected block.

Changing any of the nonvolatile bits of the control reg-

ister requires the following steps:

– Write a 02H to the Control Register to set the Write

Enable Latch (WEL). This is a volatile operation, so

there is no delay after the write. (Operation pre-

ceeded by a start and ended with a stop).

To illustrate, a sequence of writes to the device con-

sisting of [02H, 06H, 02H] will reset all of the nonvola-

tile bits in the Control Register to 0. A sequence of

[02H, 06H, 06H] will leave the nonvolatile bits

unchanged and the RWEL bit remains set.

– Write a 06H to the Control Register to set both the

bit. This is also a volatile cycle. The zeros in the data

byte are required. (Operation preceeded by a start

and ended with a stop).

SERIAL INTERFACE

Serial Interface Conventions

– Write a value to the Control Register that has all the

control bits set to the desired state. This can be rep-

resented as 0xys t01r in binary, where xy are the

WD bits, and rst are the BP bits. (Operation pre-

ceeded by a start and ended with a stop). Since this

is a nonvolatile write cycle it will take up to 10ms to

complete. The RWEL bit is reset by this cycle and

the sequence must be repeated to change the non-

volatile bits again. If bit 2 is set to ‘1’ in this third step

(0xys t11r) then the RWEL bit is set, but the WD1,

WD0, BP2, BP1 and BP0 bits remain unchanged.

Writing a second byte to the control register is not

allowed. Doing so aborts the write operation and

returns a NACK.

The device supports a bidirectional bus oriented proto-

col. The protocol defines any device that sends data

onto the bus as a transmitter, and the receiving device

as the receiver. The device controlling the transfer is

called the master and the device being controlled is

called the slave. The master always initiates data

transfers, and provides the clock for both transmit and

receive operations. Therefore, the devices in this fam-

ily operate as slaves in all applications.

Serial Clock and Data

Data states on the SDA line can change only during

SCL LOW. SDA state changes during SCL HIGH are

reserved for indicating start and stop conditions. See

Figure 5.

– A read operation occurring between any of the

previous operations will not interrupt the register

write operation.

Figure 5. Valid Data Changes on the SDA Bus

SCL

SDA

Data Stable

Data Change

Data Stable

FN8122.0

March 29, 2005

1...4 5 678 9 10...21

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