Datasheet > X4165

X4165

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
英特矽尔 - INTERSIL		监控可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数	文件大小	规格书
22页	352K
描述
CPU Supervisor with 16K EEPROM

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中文翻译

获取价格

数据手册

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X4165 数据手册

X4163, X4165

PIN CONFIGURATION

8 Ld JEDEC SOIC

8 Ld TSSOP

SCL

SDA

V_CC

S₀

S₁

SCL

SDA

V_SS

S₀

S₁

RESET/RESET

V_SS

RESET/RESET

PIN FUNCTION

Pin Pin

(SOIC) (TSSOP)

Name

S₀

Function

Device Select Input

S₁

RESET/

RESET

Reset Output. RESET/RESET is an active LOW/HIGH, open drain output which

goes active whenever V_CCfalls below the minimum V_CCsense level. It will remain

active until V_CCrises above the minimum V_CCsense level for 250ms.

RESET/RESET goes active if the Watchdog Timer is enabled and SDA remains

either HIGH or LOW longer than the selectable Watchdog time out period. A falling

edge on SDA, while SCL is HIGH, resets the Watchdog Timer. RESET/RESET

goes active on power up and remains active for 250ms after the power supply sta-

bilizes.

V_SS

Ground

SDA

Serial Data. SDA is a bidirectional pin used to transfer data into and out of the

device. It has an open drain output and may be wire ORed with other open drain

or open collector outputs. This pin requires a pull up resistor and the input buffer

is always active (not gated).

Watchdog Input. A HIGH to LOW transition on the SDA (while SCL is HIGH) restarts

the Watchdog timer. The absence of a HIGH to LOW transition within the watchdog

time out period results in RESET/RESET going active.

SCL

Serial Clock. The Serial Clock controls the serial bus timing for data input and output.

Write Protect. WP HIGH used in conjunction with WPEN bit prevents writes to

the control register.

V_CC

Supply Voltage

FN8120.1

May 12, 2006

1 2 345 6 7...22

中文翻译

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