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X28LV010JI-90 PDF预览

X28LV010JI-90

更新时间: 2024-11-26 23:29:59
品牌 Logo 应用领域
其他 - ETC 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
18页 143K
描述
x8 EEPROM

X28LV010JI-90 数据手册

 浏览型号X28LV010JI-90的Datasheet PDF文件第2页浏览型号X28LV010JI-90的Datasheet PDF文件第3页浏览型号X28LV010JI-90的Datasheet PDF文件第4页浏览型号X28LV010JI-90的Datasheet PDF文件第5页浏览型号X28LV010JI-90的Datasheet PDF文件第6页浏览型号X28LV010JI-90的Datasheet PDF文件第7页 
1M  
128K x 8 Bit  
X28LV010  
3.3 Volt, Byte Alterable E2PROM  
DESCRIPTION  
FEATURES  
• Access Time: 70, 90, 120, 150ns  
• Simple Byte and Page Write  
—Single 3.3V±10% supply  
The Xicor X28LV010 is a 128K x 8 E2PROM, fabri-  
cated with Xicor's proprietary, high performance, float-  
ing gate CMOS technology. Like all Xicor  
programmable non-volatile memories the X28LV010  
requires a single voltage supply. The X28LV010 fea-  
tures the JEDEC approved pinout for byte-wide memo-  
ries, compatible with industry standard EPROMs.  
No external high voltages or V control circuits  
PP  
—Self-timed  
• no erase before write  
• no complex programming algorithms  
• no overerase problem  
• Low Power CMOS  
—Active: 20mA  
—Standby: 20µA  
• Software Data Protection  
—Protects data against system level inadvertant  
writes  
• High Speed Page Write Capability  
• Highly Reliable Direct WriteCell  
—Endurance: 100,000 write cycles  
—Data retention: 100Years  
• Early End of Write Detection  
DATA polling  
The X28LV010 supports a 256-byte page write opera-  
tion, effectively providing a 12µs/byte write cycle and  
enabling the entire memory to be typically written in  
less than 2.5 seconds. The X28LV010 also features  
DATA Polling and Toggle Bit Polling, system software  
support schemes used to indicate the early completion  
of a write cycle. In addition, the X28LV010 supports  
Software Data Protection option.  
Xicor E2PROMs are designed and tested for applica-  
tions requiring extended endurance. Data retention is  
specified to be greater than 100 years.  
Toggle bit polling  
BLOCK DIAGRAM  
1M-Bit  
E2PROM  
Array  
X Buffers  
Latches and  
Decoder  
A –A  
8
16  
I/O Buffers  
and Latches  
Y Buffers  
Latches and  
Decoder  
A –A  
0
7
I/O –I/O  
0
7
Data Inputs/Outputs  
CE  
OE  
WE  
Control  
Logic and  
Timing  
V
CC  
SS  
V
Xicor, Inc. 2000 Patents Pending  
2000-4003 9/6/00 EP  
Characteristics subject to change without notice. 1 of 18  

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