This X25256 device has been acquired by
IC MICROSYSTEMS from Xicor; Inc.
Preliminary Information
256K
32K x 8 Bit
X25256
5MHz SPI Serial E 2PROM with Block Lock ™ Protection
FEATURES
•Packages —8-
lead XBGA
•5MHz Clock Rate
•Low Power CMOS
—8-lead SOIC (JEDEC, EIAJ)
—20-lead TSSOP
—<1µA standby current
—<5mA active current
DESCRIPTION
•2.5V To 5.5V Power Supply
•SPI Modes (0,0 & 1,1)
2
The X25256 is a CMOS 256K-bit serial E
PROM, inter-
•32K X 8 Bits
—64 byte page mode
nally organized as 32K x 8. The X25256 features a
Serial Peripheral Interface (SPI) and software protocol
™ Protection
—Protect first page, first 2 pages, first 4 pages,
allowing operation on a simple three-wire bus. The bus
signals are a clock input (SCK) plus separate data in
•Block Lock
first 8 pages, 1/4, 1/2 or all of E2
•Programmable Hardware Write Protection
(SI) and data out (SO) lines. Access to the device is
controlled through a chip select (CS) input, allowing any
PROM array
number of devices to share the same bus.
—In-circuit programmable ROM mode
•Built-In Inadvertent Write Protection
The X25256 also features two additional inputs that
provide the end user with added flexibility. By asserting
—Power-up/down protection circuitry
—Write enable latch
the HOLD input, the X25256 will ignore transitions on its
inputs, thus allowing the host to service higher priority
—Write protect pin
•Self-Timed Write Cycle
interrupts. The WP input can be used as a hardwire
input to the X25256 disabling all write attempts to the
—5ms write cycle time (typical)
•High Reliability
status register, thus providing a mechanism for limiting
end user capability of altering first page, first 2 pages, 4
—Endurance: 100,000 cycles
—Data Retention: 100 Years
—ESD protection: 2000V on all pins
pages, 8 pages, 0, 1/4, 1/2 or all of the memory.
FUNCTIONAL DIAGRAM
Write
Protect
Status
Register
Logic
32K Byte
Array
128
128 X 512
SO
Command
SI
And
Decode
128
X-Decode
Protect
Logic
SCK
128 X 512
248 X 512
Control
Logic
CS
HOLD
248
4
256 X 512
4 X 512
2 X 512
1 X 512
1 X 512
Write
2
1
1
Control
And
Timing
WP
Logic
64
8
Y Decode
Data Register
™ and Block Lock™ Protection is a trademark of Xicor, Inc.
Characteristics subject to change without notice. 1 of 17
www.icmic.com