X25043/45
PRINCIPLES OF OPERATION
The Write-In-Process (WIP) bit indicates whether the
X25043/45 is busy with a write operation. When set to a
“1”, a write is in progress, when set to a “0”, no write is
in progress. During a write, all other bits are set to “1”.
The WIP bit is read-only.
The X25043/45 is a 512 x 8 E2PROM designed to
interface directly with the synchronous serial peripheral
interface(SPI)ofmanypopularmicrocontrollerfamilies.
The X25043/45 contains an 8-bit instruction register. It
is accessed via the SI input, with data being clocked in
on the rising SCK. CS must beLOW and WP input must
be HIGH during the entire operation. The X25043/45
monitors the bus and provides a RESET/RESET output
if there is no bus activity within the preset time period.
The Write Enable Latch (WEL) bit indicates the status of
the“writeenable”latch.Whensettoa“1”,thelatchisset,
when set to a “0”, the latch is reset. The WEL bit is read-
only and is set by the WREN instruction and reset by
WRDI instruction or successful completion of a write
cycle.
Table 1 contains a list of the instructions and their
operation codes. All instructions, addresses and data
are transferred MSB first. Bit 3 of the Read and Write
instructions contain the higher order address bit, A8.
The Block Protect (BL0 and BL1) bits indicate the extent
ofprotectionemployed.Thesenonvolatilebitsaresetby
issuing the WRSR instruction and allows the user to
select one of four levels of protection and program the
watchdog timer. The X25043/45 is divided into four
1024-bit segments. One, two, or all four of the segments
may be locked. That is, the user may read the segments
but will be unable to alter (write) data within the selected
segments. The partitioning is controlled as illustrated
below with the state of BL1 and BL0.
DatainputissampledonthefirstrisingedgeofSCKafter
CS goes LOW. SCK is static, allowing the user to stop
the clock and then resume operations.
Write Enable Latch
The X25043/45 contains a “write enable” latch. This
latch must be SET before a write operation will be
completed internally. The WREN instruction will set the
latch and the WRDI instruction will reset the latch. This
latch is automatically reset upon a power-up condition
and after the completion of a byte, page, or status
register write cycle. The latch is also reset if WP is
brought LOW.
Status Register Bits
Array Addresses
Protected
BL1
BL0
0
0
1
1
0
1
0
1
None
$180–$1FF
$100–$1FF
$000–$1FF
Status Register
3844 PGM T04
The RDSR instruction provides access to the status
register. The status register may be read at any time,
even during a write cycle. The status register is format-
ted as follows:
The Watchdog Timer (WD0 and WD1) bits allow setting
of the watchdog time-out function as shown in the table
below. These nonvolatile bits are set by issuing the
WRSR instruction.
7
X
6
5
4
3
2
BL0
1
0
Status Register Bits
Watchdog Time-out
(Typical)
X WD1 WD0 BL1
WEL WIP
WD1
WD0
3844 PGM T02
0
0
1
1
0
1
0
1
1.4 Seconds
600 Milliseconds
200 Milliseconds
When issuing, WREN, WRDI and RDSR commands, it
is not necessary to send a byte address or data.
Disabled
3844 PGM T03
3
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