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X25057

更新时间: 2024-11-13 22:41:23
品牌 Logo 应用领域
XICOR 可编程只读存储器
页数 文件大小 规格书
16页 76K
描述
5MHz Low Power SPI Serial E 2 PROM with IDLock⑩ Memory

X25057 数据手册

 浏览型号X25057的Datasheet PDF文件第2页浏览型号X25057的Datasheet PDF文件第3页浏览型号X25057的Datasheet PDF文件第4页浏览型号X25057的Datasheet PDF文件第5页浏览型号X25057的Datasheet PDF文件第6页浏览型号X25057的Datasheet PDF文件第7页 
4K  
512 x 8 Bit  
X25057  
5MHz Low Power SPI Serial E2PROM with IDLock™ Memory  
DESCRIPTION  
FEATURES  
TheX25057isaCMOS4K-bitserialE2PROM,internally  
organized as 512 x 8. The X25057 features a Serial  
Peripheral Interface (SPI) and software protocol  
allowing operation on a simple four-wire bus. The bus  
signals are a clock input (SCK) plus separate data in (SI)  
and data out (SO) lines. Access to the device is  
controlled through a chip select (CS) input, allowing any  
number of devices to share the same bus.  
• 5MHz Clock Rate  
• IDLock™ Memory  
—IDLock First or Last Page, Any 1/4 or Lower 1/2  
of E2PROM Array  
• Low Power CMOS  
—<1µA Standby Current  
—<3mA Active Current during Write  
—<400µA Active Current during Read  
• 1.8V to 3.6V, 2.7V-5.5V or 4.5V to 5.5V Operation  
• Built-in Inadvertent Write Protection  
Power-Up/Power-Down Protection Circuitry  
—Write Enable Latch  
—Write Protect Pin  
• SPI Modes (0,0 & 1,1)  
• 512 x 8 Bits  
—16 Byte Page Mode  
• Self-Timed Write Cycle  
—5ms Write Cycle Time (Typical)  
• High Reliability  
—Endurance: 100,000 Cycles/Byte  
—Data Retention: 100Years  
—ESD: 2000V on all pins  
• 8-Lead MSOP Package  
IDLock is a programmable locking mechanism which  
allows the user to lock system ID and parametric data in  
different portions of the E2PROM memory space,  
ranging from as little as one page to as much as 1/2 of  
the total array. The X25057 also features a WP pin that  
can be used for hardwire protection of the part, disabling  
all write attempts, as well as a Write Enable Latch that  
must be set before a write operation can be initiated.  
The X25057 utilizes Xicor’s proprietary Direct WriteTM  
cell, providing a minimum endurance of 100,000 cycles  
per byte and a minimum data retention of 100 years.  
• 8-Lead TSSOP Package  
• 8-Lead SOIC Package  
• 8-Lead PDIP Package  
FUNCTIONAL DIAGRAM  
DATA REGISTER  
SI  
Y DECODE LOGIC  
SO  
16  
8
COMMAND  
DECODE  
AND  
CONTROL  
LOGIC  
X
32  
SCK  
CS  
DECODE  
LOGIC  
4K E2PROM  
ARRAY  
(512 x 8)  
HIGH VOLTAGE  
CONTROL  
WP  
WRITE CONTROL LOGIC  
7033 FRM F01  
Xicor, Inc. 1994 – 1997 Patents Pending  
7033-1.1 5/8/97 T1/C0/D0 SH  
Characteristics subject to change without notice  
1

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