Datasheet > X24C02B

X24C02B

更新时间： 2024-01-28 14:41:37

品牌	Logo	应用领域
ICMIC		可编程只读存储器
页数	文件大小	规格书
16页	294K
描述
Serial E2PROM

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中文翻译

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技术参数
数据手册

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X24C02B 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
零件包装代码：	DIP	包装说明：	DIP,
针数：	8	Reach Compliance Code：	unknown
ECCN代码：	3A001.A.2.C	HTS代码：	8542.32.00.51
风险等级：	5.76	最大时钟频率 (fCLK)：	0.1 MHz
JESD-30 代码：	R-PDIP-T8	长度：	10.03 mm
内存密度：	2048 bit	内存集成电路类型：	EEPROM
内存宽度：	8	湿度敏感等级：	3
功能数量：	1	端子数量：	8
字数：	256 words	字数代码：	256
工作模式：	SYNCHRONOUS	最高工作温度：	125 °C
最低工作温度：	-55 °C	组织：	256X8
封装主体材料：	PLASTIC/EPOXY	封装代码：	DIP
封装形状：	RECTANGULAR	封装形式：	IN-LINE
并行/串行：	SERIAL	峰值回流温度（摄氏度）：	NOT SPECIFIED
认证状态：	Not Qualified	座面最大高度：	4.07 mm
串行总线类型：	I2C	最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V	标称供电电压 (Vsup)：	5 V
表面贴装：	NO	技术：	CMOS
温度等级：	MILITARY	端子形式：	THROUGH-HOLE
端子节距：	2.54 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	7.62 mm
最长写入周期时间 (tWC)：	10 ms	Base Number Matches：	1

X24C02B 数据手册

X24C02

Current Address Read

Internally the X24C02 contains an address counter that

maintains the address of the last word accessed,

Random Read

Random read operations allow the master to access any

memory location in a random manner. Prior to issuing

incremented by one. Therefore, if the last access (either

a read or write) was to address n, the next read operation

the slave address with the R/W bit set to one, the master

must first perform a “dummy” write operation. The master

would access data from address n + 1. Upon receipt of the

slave address with the R/W bit set to one, the

ter issues the start condition, and the slave address

followed by the word address it is to read. After the word

X24C02 issues an acknowledge and transmits the eight bit

word during the next eight clock cycles. The master

address acknowledge, the master immediately reissues

the start condition and the slave address with the R/W bit

terminates this transmission by issuing a stop condition,

omitting the ninth clock cycle acknowledge. Refer to

set to one. This will be followed by an acknowledge from

the X24C02 and then by the eight bit word. The master

Figure 7 for the sequence of address, acknowledge and

data transfer.

terminates this transmission by issuing a stop condition,

omitting the ninth clock cycle acknowledge. Refer to

Figure 8 for the address, acknowledge and data transfer

sequence.

Figure 7. Current Address Read

SLAVE

ADDRESS

BUS ACTIVITY:

MASTER

DATA

SDA LINE

BUS ACTIVITY:

X24C02

3838 FHD F13

Figure 8. Random Read

SLAVE

ADDRESS

WORD

ADDRESS n

SLAVE

ADDRESS

BUS ACTIVITY:

MASTER

DATA n

SDA LINE

BUS ACTIVITY:

X24C02

3838 FHD F14

1...4 5 678 9 10...16

中文翻译

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与X24C02B相关器件

型号	品牌	描述	获取价格	数据表
X24C02BG	ICMIC	Serial E2PROM	获取价格
X24C02BM	ICMIC	Serial E2PROM	获取价格
X24C02BP	ICMIC	Serial E2PROM	获取价格
X24C02BS8	ICMIC	Serial E2PROM	获取价格
X24C02C	ICMIC	Serial E2PROM	获取价格
X24C02CG	ICMIC	Serial E2PROM	获取价格