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X24C01SM-3 PDF预览

X24C01SM-3

更新时间: 2024-01-05 23:53:34
品牌 Logo 应用领域
XICOR 内存集成电路光电二极管可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
页数 文件大小 规格书
14页 58K
描述
Serial E2PROM

X24C01SM-3 数据手册

 浏览型号X24C01SM-3的Datasheet PDF文件第1页浏览型号X24C01SM-3的Datasheet PDF文件第2页浏览型号X24C01SM-3的Datasheet PDF文件第4页浏览型号X24C01SM-3的Datasheet PDF文件第5页浏览型号X24C01SM-3的Datasheet PDF文件第6页浏览型号X24C01SM-3的Datasheet PDF文件第7页 
X24C01  
DEVICE OPERATION  
Clock and Data Conventions  
DatastatesontheSDAlinecanchangeonlyduringSCL  
LOW. SDA state changes during SCL HIGH are re-  
served for indicating start and stop conditions. Refer to  
Figures 1 and 2.  
The X24C01 supports a bidirectional bus oriented pro-  
tocol. The protocol defines any device that sends data  
ontothebusasatransmitterandthereceivingdeviceas  
the receiver. The device controlling the transfer is a  
master and the device being controlled is the slave. The  
master will always initiate data transfers and provide the  
clock for both transmit and receive operations. There-  
fore, the X24C01 will be considered a slave in all  
applications.  
Start Condition  
All commands are preceded by the start condition,  
which is a HIGH to LOW transition of SDA when SCL is  
HIGH. The X24C01 continuously monitors the SDA and  
SCL lines for the start condition and will not respond to  
any command until this condition has been met.  
Figure 1. Data Validity  
SCL  
SDA  
DATA STABLE  
DATA  
CHANGE  
3837 FHD F06  
3

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