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X1228V14Z PDF预览

X1228V14Z

更新时间： 2024-01-21 10:54:30
品牌 Logo 应用领域
英特矽尔 - INTERSIL 监控可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
页数 文件大小 规格书
29页 427K
描述
Real Time Clock/Calendar/CPU Supervisor with EEPROM

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中文翻译

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X1228V14Z 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：TSSOP包装说明：TSSOP, TSSOP14,.25
针数：14Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.62最大时钟频率：0.032 MHz
信息访问方法：I2C中断能力：Y
JESD-30 代码：R-PDSO-G14JESD-609代码：e3
长度：5 mm湿度敏感等级：1
端子数量：14计时器数量：1
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP14,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：260
电源：3/5 V认证状态：Not Qualified
座面最大高度：1.2 mm子类别：Timer or RTC
最大供电电压：5.5 V最小供电电压：2.7 V
标称供电电压：5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：MATTE TIN端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
最短时间：SECONDS处于峰值回流温度下的最长时间：40
易失性：YES宽度：4.4 mm
uPs/uCs/外围集成电路类型：TIMER, REAL TIME CLOCKBase Number Matches：1

X1228V14Z 数据手册

 浏览型号X1228V14Z的Datasheet PDF文件第6页浏览型号X1228V14Z的Datasheet PDF文件第7页浏览型号X1228V14Z的Datasheet PDF文件第8页浏览型号X1228V14Z的Datasheet PDF文件第10页浏览型号X1228V14Z的Datasheet PDF文件第11页浏览型号X1228V14Z的Datasheet PDF文件第12页 
X1228  
DESCRIPTION  
PIN DESCRIPTIONS  
X1228  
14-Pin TSSOP/SOIC  
The X1228 device is a Real Time Clock with  
clock/calendar, two polled alarms with integrated 512x8  
EEPROM, oscillator compensation, CPU Supervisor  
(POR/LVS and WDT) and battery backup switch.  
VCC  
1
2
3
4
5
6
7
X1  
X2  
NC  
NC  
NC  
14  
13  
12  
11  
10  
9
VBACK  
PHZ/IRQ  
NC  
The oscillator uses an external, low-cost 32.768kHz  
crystal. All compensation and trim components are  
integrated on the chip. This eliminates several external  
discrete components and a trim capacitor, saving  
board area and component cost.  
NC  
SCL  
SDA  
RESET  
8
VSS  
NC = No internal connection  
Serial Clock (SCL)  
The Real-Time Clock keeps track of time with  
separate registers for Hours, Minutes, Seconds. The  
Calendar has separate registers for Date, Month, Year  
and Day-of-week. The calendar is correct through  
2099, with automatic leap year correction.  
The SCL input is used to clock all data into and out of  
the device. The input buffer on this pin is always active  
(not gated).  
Serial Data (SDA)  
SDA is a bidirectional pin used to transfer data into  
and out of the device. It has an open drain output and  
may be wire ORed with other open drain or open col-  
lector outputs. The input buffer is always active (not  
gated).  
The powerful Dual Alarms can be set to any  
Clock/Calendar value for a match. For instance, every  
minute, every Tuesday, or 5:23 AM on March 21. The  
alarms can be polled in the Status Register or provide  
a hardware interrupt (IRQ Pin). There is a repeat  
mode for the alarms allowing a periodic interrupt.  
An open drain output requires the use of a pull-up  
resistor. The output circuitry controls the fall time of  
the output signal with the use of a slope controlled  
pull-down. The circuit is designed for 400kHz 2-wire  
interface speeds.  
The PHZ/IRQ pin may be software selected to provide  
a frequency output of 1 Hz, 4096 Hz, or 32,768 Hz.  
The X1228 device integrates CPU Supervisor func-  
tions and a Battery Switch. There is a Power-On Reset  
(RESET output) with typically 250 ms delay from  
power-on. It will also assert RESET when Vcc goes  
V
BACK  
This input provides a backup supply voltage to the  
device. V supplies power to the device in the  
below the specified threshold. The V  
threshold is  
trip  
BACK  
user repro-grammable. There is a WatchDog Timer  
(WDT) with 3 selectable time-out periods (0.25s,  
0.75s, 1.75s) and a disabled setting. The watchdog  
activates the RESET pin when it expires.  
event the V supply fails. This pin can be connected  
to a battery, a Supercap or tied to ground if not used.  
CC  
RESET Output – RESET  
This is a reset signal output. This signal notifies a host  
processor that the watchdog time period has expired or  
The device offers a backup power input pin. This  
V
pin allows the device to be backed up by  
BACK  
that the voltage has dropped below a fixed V  
thresh-  
TRIP  
battery or SuperCap. The entire X1228 device is fully  
operational from 2.7 to 5.5 volts and the  
clock/calendar portion of the X1228 device remains  
fully operational down to 1.8 volts (Standby Mode).  
old. It is an open drain active LOW output. Recom-  
mended value for the pullup resistor is 5kΩ. If unused, tie  
to ground.  
Programmable Frequency/Interrupt Output – PHZ/IRQ  
The X1228 device provides 4K bits of EEPROM with 8  
modes of BlockLock™ control. The BlockLock allows a  
safe, secure memory for critical user and configuration  
data, while allowing a large user storage area.  
This is either an output from the internal oscillator or an  
interrupt signal output. It is a CMOS output.  
When used as frequency output, this signal has a fre-  
quency of 32.768kHz, 4096Hz, 1Hz or inactive.  
When used as interrupt output, this signal notifies a  
host processor that an alarm has occurred and an  
action is required. It is an active LOW output.  
The control bits for this function are FO1 and FO0 and  
are found in address 0011h of the Clock Control Mem-  
ory map. See “Programmable Frequency Output  
Bits—FO1, FO0” on page 14.  
FN8100.2  
9
October 17, 2005  
1...6789101112...29

中文翻译

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