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X1241V8-2.7A PDF预览

X1241V8-2.7A

更新时间: 2024-01-07 14:29:46
品牌 Logo 应用领域
瑞萨 - RENESAS 光电二极管
页数 文件大小 规格书
22页 195K
描述
Real Time Clock, Volatile, 0 Timer(s), CMOS, PDSO8, PLASTIC, TSSOP-8

X1241V8-2.7A 数据手册

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Preliminary Information  
16K  
2-WireRTC  
X1241  
Real Time Clock/Calendar/CPU Supervisor with EEPROM  
FEATURES  
DESCRIPTION  
• Programmable low voltage reset  
• Selectable watchdog timer (1.75s, 750ms,  
250ms, off)  
The X1241 is a Real Time Clock with clock/calendar  
circuits and a selectable watchdog timer. The dual port  
clock register allows the clock to operate, without loss  
of accuracy, even during read and write operations.  
• 2-wire interface interoperable with I2C  
—400kHz data transfer rate  
The clock/calendar provides functionality that is con-  
trollable and readable through a set of registers. The  
clock, using a low cost 32.768kHz crystal input, accu-  
rately tracks the time in seconds, minutes, hours, date,  
day, month and years. It has leap year correction,  
automatic adjustment for the year 2000 and months  
with less than 31 days.  
• Secondary power supply input with internal  
switch-over circuitry  
• 2Kbytes of EEPROM  
—64-byte page write mode  
—3-bit block lock  
• Low power CMOS  
—<1µA operating current  
—<3mA active current during program  
—<400µA active current during data read  
• Single byte write capability  
• Typical nonvolatile write cycle time: 5ms  
• High reliability  
The device offers a backup power input pin. This  
V
pin allows the device to be backed up by a non-  
BACK  
rechargeable battery. The RTC is fully operational from  
1.8 to 5.5 volts.  
The X1241 provides a 2Kbyte EEPROM array, giving a  
safe, secure memory for critical user and configuration  
data. This memory is unaffected by complete failure of  
the main and backup supplies.  
• Small package options  
—8-lead SOIC package, 8-lead TSSOP package  
BLOCK DIAGRAM  
X1  
Timer  
Calendar  
Logic  
Frequency  
Divider  
1Hz  
32.768kHz  
Oscillator  
Time  
X2  
Keeping  
Registers  
(SRAM)  
Control  
Registers  
(EEPROM)  
Control  
Decode  
Logic  
Status  
Register  
(SRAM)  
SCL  
SDA  
Serial  
Interface  
Decoder  
16Kbit  
EEPROM  
Array  
8
Watchdog  
Timer  
Low Voltage  
Reset  
RESET  
Characteristics subject to change without notice. 1 of 22  
REV 1.1.3 2/13/01  
www.xicor.com  

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