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WF512K32N-60G4C5 PDF预览

WF512K32N-60G4C5

更新时间: 2024-11-14 22:32:23
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其他 - ETC 闪存
页数 文件大小 规格书
15页 162K
描述
512Kx32 5V FLASH MODULE, SMD 5962-94612

WF512K32N-60G4C5 数据手册

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WF512K32-XXX5  
HI-RELIABILITY PRODUCT  
512Kx32 5V FLASH MODULE, SMD 5962-94612  
FEATURES  
Access Times of 60, 70, 90, 120, 150ns  
Organized as 512Kx32  
Packaging  
Commercial, Industrial and Military Temperature Ranges  
5 Volt Programming. 5V ±10% Supply.  
• 66 pin, PGA Type, 1.075" square, Hermetic  
Ceramic HIP (Package 400(1))  
Low Power CMOS, 6.5mA Standby  
• 68 lead, 40mm, Low Capacitance Hermetic CQFP  
(Package 501)  
Embedded Erase and Program Algorithms  
TTL Compatible Inputs and CMOS Outputs  
Built-in Decoupling Caps for Low Noise Operation  
Page Program Operation and Internal Program Control Time  
• 68 lead, 40mm, Low Profile 3.5mm (0.140"), CQFP  
(Package 502)  
• 68 lead, 22.4mm (0.880") Low Profile CQFP (G2U), 3.5mm  
(0.140") high, (Package 510)  
Weight  
WF512K32-XG2UX5 - 8 grams typical  
WF512K32-XH1X5 - 13 grams typical  
WF512K32-XG4X5 - 20 grams typical  
WF512K32-XG4TX5 - 20 grams typical  
WF512K32-XG1UX5 - 5 grams typical  
• 68 lead, 23.9mm (0.940") Low Profile CQFP (G1U), 3.5mm  
(0.140") high, (Package 519)  
100,000 Erase/Program Cycles Minimum  
Sector Architecture  
• 8 equal size sectors of 64KBytes each  
• Any combination of sectors can be concurrently erased.  
Also supports full chip erase  
1. Call factory for PGA type (HIP) package options.  
Note: See Flash Programming Application Note 4M5 for algorithms.  
FIG. 1 PIN CONFIGURATION FOR WF512K32N-XH1X5  
PIN DESCRIPTION  
TOP VIEW  
1
12  
23  
34  
45  
56  
I/O0-31 Data Inputs/Outputs  
I/O  
I/O  
8
9
WE  
2
I/O15  
I/O14  
I/O13  
I/O12  
OE  
I/O24  
I/O25  
I/O26  
V
CC  
I/O31  
I/O30  
I/O29  
I/O28  
A0-18  
WE1-4  
CS1-4  
OE  
Address Inputs  
Write Enables  
Chip Selects  
Output Enable  
Power Supply  
Ground  
CS2  
CS  
4
I/O10  
GND  
I/O11  
WE  
4
A
A
A
A
A
14  
16  
11  
0
A
7
I/O27  
VCC  
A
A
A
V
10  
9
A12  
A
A
4
5
6
3
3
A1  
A2  
A3  
GND  
NC  
Not Connected  
A
17  
NC  
15  
CC  
WE1  
A13  
A
BLOCK DIAGRAM  
WE3 CS3  
WE4 CS4  
18  
I/O  
I/O  
I/O  
I/O  
7
A
8
WE  
CS  
I/O23  
I/O22  
I/O21  
I/O20  
WE1 CS1  
WE2 CS2  
OE  
A
0-18  
I/O  
I/O  
I/O  
0
1
2
CS  
NC  
I/O  
1
6
I/O16  
I/O17  
I/O18  
512K x 8  
512K x 8  
512K x 8  
512K x 8  
5
4
GND  
I/O19  
3
8
8
8
8
11  
22  
33  
44  
55  
66  
I/O16-23  
I/O24-31  
I/O0-7  
I/O8-15  
April 2001 Rev. 4  
1
White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520  

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