Datasheet > WF2M32U-150HI5

WF2M32U-150HI5

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
WEDC		闪存
页数	文件大小	规格书
15页	750K
描述
2Mx32 5V Flash Module

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WF2M32U-150HI5 数据手册

WF2M32-XXX5

White Electronic Designs

2Mx32 5V Flash Module

FEATURES

ꢀ

Access Time of 90, 120, 150ns

ꢀ

Organized as 2Mx32

Commercial, Industrial, and Military

Temperature Ranges

5 Volt Read and Write. 5V 10ꢀ Supply.

Low Power CMOS

Data# Polling and Toggle Bit feature for detection of

program or erase cycle completion.

Supports reading or programming data to a sector

not being erased.

RESET# pin resets internal state machine to the

read mode.

Built in Decoupling Caps and Multiple Ground Pins

for Low Noise Operation, Separate Power and

Ground Planes to improve noise immunity

Packaging:

• 66 pin, PGA Type, 1.185" square, Hermetic

Ceramic HIP (Package 401).

ꢀ

• 68 lead, Hermetic CQFP (G2U), 22.4mm (0.880")

square (Package 510) 3.56mm (0.140") height.

Designed to ﬁt JEDEC 68 lead 0.990" CQFJ

footprint (FIGURE 3)

ꢀ

Sector Architecture

• 32 equal size sectors of 64KBytes per each 2Mx8

chip

• Any combination of sectors can be erased. Also

supports full chip erase.

Minimum 100,000 Write/Erase Cycles Minimum

* This product is subject to change without notice.

Note: For programming information refer to Flash Programming 16M5 Application Note.

FIGURE 1 – PIN CONFIGURATION FOR WF2M32-XHX5

Top View

Pin Description

I/O0-31

A0-20

WE1-4#

CS1-4#

OE#

Data Inputs/Outputs

Address Inputs

Write Enables

Chip Selects

Output Enable

Power Supply

Ground

I/O8

I/O9

I/O10

A14

A16

A11

WE2#

CS2#

GND

I/O11

A10

I/O15

I/O24

I/O25

I/O26

VCC

CS4#

WE4#

I/O27

I/O31

I/O30

I/O29

I/O28

I/O14

I/O13

I/O12

OE#

A17

VCC

GND

A12

Block Diagram

WE1# CS1#

WE2# CS2#

WE3# CS3#

WE4# CS4#

2M x 8

A20

OE#

A0-20

A15

WE1#

I/O7

A13

2M x 8

A18

I/O0

I/O1

I/O2

VCC

CS1#

A19

WE3#

CS3#

GND

I/O19

I/O23

I/O22

I/O21

I/O20

I/O6

I/O16

I/O17

I/O18

I/O5

I/O16-23

I/O24-31

I/O0-7

I/O8-15

I/O3

I/O4

RESET# internally tied to V_CCin the HIP package for this pin con-

ﬁguration. See Alternate Pin Conﬁguration with RESET# tied to pin

12 for system control of reset (FIGURE 10, page 11).

October 2004

Rev. 5

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

12 3 4 5 6 7...15

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