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WF2M32-XHX5 PDF预览

WF2M32-XHX5

更新时间: 2024-02-04 16:35:10
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Flash MCP

WF2M32-XHX5 数据手册

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WF2M32-XXX5  
White Electronic Designs  
PRELIMINARY*  
2Mx32 5V Flash Module  
FEATURES  
„ Commercial, Industrial, and Military  
„ Access Time of 90, 120, 150ns  
„ Packaging:  
Temperature Ranges  
„ 5 Volt Read and Write. 5V ± 10% Supply.  
„ Low Power CMOS  
• 66 pin, PGA Type, 1.185" square, Hermetic  
Ceramic HIP (Package 401).  
„ Data Polling and Toggle Bit feature for detection  
• 68 lead, Hermetic CQFP (G2U), 22.4mm  
(0.880") square (Package 510) 3.56mm  
(0.140") height. Designed to fit JEDEC 68 lead  
0.990" CQFJ footprint (Fig. 3)  
of program or erase cycle completion.  
„ Supports reading or programming data to a  
sector not being erased.  
„ Sector Architecture  
„ RESET pin resets internal state machine to the  
read mode.  
• 32 equal size sectors of 64KBytes per each  
2Mx8 chip  
„ Built in Decoupling Caps and Multiple Ground  
Pins for Low Noise Operation, Separate Power  
and Ground Planes to improve noise immunity  
• Any combination of sectors can be erased.  
Also supports full chip erase.  
„ Minimum 100,000 Write/Erase Cycles Minimum  
„ Organized as 2Mx32  
* This data sheet describes a product under development, not fully characterized,  
and is subject to change without notice.  
Note:  
For programming information refer to Flash Programming 16M5 Application  
Note.  
FIG. 1 PIN CONFIGURATION FOR WF2M32-XHX5  
PINDESCRIPTION  
I/O0-31 Data Inputs/Outputs  
TOP VIEW  
A0-20  
WE1-4  
CS1-4  
OE  
VCC  
GND  
Address Inputs  
Write Enables  
Chip Selects  
Output Enable  
Power Supply  
Ground  
1
12  
23  
34  
45  
56  
I/O  
I/O  
8
9
WE  
CS  
2
I/O15  
I/O14  
I/O13  
I/O12  
OE  
I/O24  
I/O25  
I/O26  
V
CC  
I/O31  
I/O30  
I/O29  
I/O28  
2
CS  
4
4
I/O10  
GND  
I/O11  
WE  
A
A
A
A
A
14  
16  
11  
0
A
7
I/O27  
A
A
A
V
10  
9
A
A
A
12  
20  
13  
A
A
4
5
6
3
3
A
A
A
1
2
3
BLOCKDIAGRAM  
WE3 CS3  
WE4 CS4  
WE1 CS1  
WE2 CS2  
A
17  
OE  
A0-20  
15  
CC  
WE  
1
A
18  
I/O  
I/O  
I/O  
I/O  
7
A
8
WE  
CS  
I/O23  
I/O22  
I/O21  
I/O20  
2M x 8  
2M x 8  
2M x 8  
2M x 8  
I/O  
I/O  
I/O  
0
1
2
CS  
1
6
I/O16  
I/O17  
I/O18  
8
8
8
8
A
19  
5
4
GND  
I/O19  
I/O  
3
I/O16-23  
I/O24-31  
I/O0-7  
I/O8-15  
11  
22  
33  
44  
55  
66  
RESET internally tied to Vcc in the HIP package for this pin  
configuration. See Alternate Pin Configuration with RESET tied  
to pin 12 for system control of reset (Fig. 10, page 11).  
January2004Rev.4  
1
WhiteElectronicDesignsCorporation(602)437-1520•  

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