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WF2M32U-90G2UE5 PDF预览

WF2M32U-90G2UE5

更新时间: 2023-02-26 12:52:09
品牌 Logo 应用领域
WEDC 内存集成电路
页数 文件大小 规格书
14页 213K
描述
Flash Module, 2MX32, 90ns, CQFP68, 22.40 X 22.40 MM, 3.56 MM HEIGHT, HERMATIC SEALED, CERAMIC, QFP-68

WF2M32U-90G2UE5 技术参数

是否Rohs认证: 不符合生命周期:Transferred
包装说明:22.40 X 22.40 MM, 3.56 MM HEIGHT, HERMATIC SEALED, CERAMIC, QFP-68Reach Compliance Code:unknown
风险等级:5.75最长访问时间:90 ns
JESD-30 代码:S-CQFP-G68JESD-609代码:e0
长度:22.36 mm内存密度:67108864 bit
内存集成电路类型:FLASH MODULE内存宽度:32
功能数量:1端子数量:68
字数:2097152 words字数代码:2000000
工作模式:ASYNCHRONOUS最高工作温度:100 °C
最低工作温度:-55 °C组织:2MX32
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:QFP
封装形状:SQUARE封装形式:FLATPACK
并行/串行:PARALLEL峰值回流温度(摄氏度):NOT SPECIFIED
编程电压:5 V认证状态:Not Qualified
座面最大高度:3.51 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:OTHER端子面层:TIN LEAD
端子形式:GULL WING端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
类型:NOR TYPE宽度:22.36 mm
Base Number Matches:1

WF2M32U-90G2UE5 数据手册

 浏览型号WF2M32U-90G2UE5的Datasheet PDF文件第2页浏览型号WF2M32U-90G2UE5的Datasheet PDF文件第3页浏览型号WF2M32U-90G2UE5的Datasheet PDF文件第4页浏览型号WF2M32U-90G2UE5的Datasheet PDF文件第5页浏览型号WF2M32U-90G2UE5的Datasheet PDF文件第6页浏览型号WF2M32U-90G2UE5的Datasheet PDF文件第7页 
WF2M32-XXX5  
White Electronic Designs  
PRELIMINARY*  
2Mx32 5V Flash Module  
FEATURES  
Commercial, Industrial, and Extended Tempera-  
Access Time of 90, 120, 150ns  
ture Ranges  
Packaging:  
5 Volt Read and Write( 5V ± 10% Supply(  
Low Power CMOS  
• 66 pin, PGA Type, 1(185" square, Hermetic  
Ceramic HIP ꢀPackage 401)(  
Data Polling and Toggle Bit feature for detection  
• 68 lead, Hermetic CQFP ꢀG2U), 22(4mm  
ꢀ0(880") square ꢀPackage 510) 3(56mm  
ꢀ0(140") height( Designed to fit JEDEC 68 lead  
0(990" CQFJ footprint ꢀFig( 3)  
of program or erase cycle completion(  
Supports reading or programming data to a  
sector not being erased(  
Sector Architecture  
RESET pin resets internal state machine to the  
read mode(  
• 32 equal size sectors of 64KBytes per each  
2Mx8 chip  
Built in Decoupling Caps and Multiple Ground  
Pins for Low Noise Operation, Separate Power  
and Ground Planes to improve noise immunity  
• Any combination of sectors can be erased(  
Also supports full chip erase(  
* This data sheet describes a product under development, not fully characterized,  
and is subject to change without noticeꢀ  
Note:  
For programming information refer to Flash Programming 16M5 Application  
Note#  
Minimum 100,000 Write/Erase Cycles Minimum  
Organized as 2Mx32  
FIGꢀ 1 PIN CONFIGURATION FOR WF2M32-XHX5  
PINDESCRIPTION  
TOP VIEW  
I/O0-31 Data Inputs/Outputs  
A0-20  
WE1-4  
CS1-4  
OE  
Address Inputs  
Write Enables  
Chip Selects  
Output Enable  
Power Supply  
Ground  
1
12  
23  
34  
45  
56  
I/O  
I/O  
8
9
WE  
CS  
2
I/O15  
I/O14  
I/O13  
I/O12  
OE  
I/O24  
I/O25  
I/O26  
V
CC  
I/O31  
I/O30  
I/O29  
I/O28  
2
CS  
4
4
VCC  
GND  
I/O10  
GND  
I/O11  
WE  
A
A
A
A
A
14  
16  
11  
0
A
7
I/O27  
A
A
A
V
10  
A12  
A20  
A13  
A
A
4
5
6
3
3
A1  
A2  
A3  
BLOCKDIAGRAM  
WE3 CS3  
WE4 CS4  
WE1 CS1  
WE2 CS2  
9
A17  
OE  
A0-20  
15  
CC  
WE  
1
A
18  
I/O  
I/O  
I/O  
I/O  
7
A
8
WE  
CS  
I/O23  
I/O22  
I/O21  
I/O20  
2M x 8  
2M x 8  
2M x 8  
2M x 8  
I/O  
I/O  
I/O  
0
1
2
CS1  
6
I/O16  
I/O17  
I/O18  
8
8
8
8
A19  
5
4
GND  
I/O19  
I/O  
3
I/O16-23  
I/O24-31  
I/O0-7  
I/O8-15  
11  
22  
33  
44  
55  
66  
RESET internally tied to Vcc in the HIP package for this pin  
configurationꢀ See Alternate Pin Configuration with RESET tied  
to pin 12 for system control of reset (Figꢀ 10, page 11)ꢀ  
December2003 Rev#4  
1
WhiteElectronicDesignsCorporation•(602)437-1520•  

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