Datasheet > WEDPN16M64VR-66BC

WEDPN16M64VR-66BC

更新时间： 2024-01-22 20:52:38

品牌	Logo	应用领域
WEDC		时钟动态存储器内存集成电路
页数	文件大小	规格书
15页	258K
描述
Synchronous DRAM Module, 16MX64, 7.5ns, CMOS, PBGA219, 32 X 25 MM, PLASTIC, BGA-219

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WEDPN16M64VR-66BC 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Transferred	零件包装代码：	BGA
包装说明：	BGA,	针数：	219
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.32.00.32	风险等级：	5.29
访问模式：	FOUR BANK PAGE BURST	最长访问时间：	7.5 ns
其他特性：	AUTO/SELF REFRESH	备用内存宽度：	32
JESD-30 代码：	R-PBGA-B219	内存密度：	1073741824 bit
内存集成电路类型：	SYNCHRONOUS DRAM MODULE	内存宽度：	64
功能数量：	1	端口数量：	1
端子数量：	219	字数：	16777216 words
字数代码：	16000000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	16MX64	封装主体材料：	PLASTIC/EPOXY
封装代码：	BGA	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY	峰值回流温度（摄氏度）：	NOT SPECIFIED
认证状态：	Not Qualified	自我刷新：	YES
最大供电电压 (Vsup)：	3.6 V	最小供电电压 (Vsup)：	3 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子形式：	BALL	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	NOT SPECIFIED	Base Number Matches：	1

WEDPN16M64VR-66BC 数据手册

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WEDPN16M64VR-XBX

White Electronic Designs

16MX64 REGISTERED SYNCHRONOUS DRAM*

GENERAL DESCRIPTION

FEATURES

The 128MByte (1Gb) SDRAM is a high-speed CMOS,

dynamic random-access, memory using 4 chips containing

268,435,456 bits. Each chip is internally conﬁgured as a

quad-bank DRAM with a synchronous interface. Each of

the chip’s 67,108,864-bit banks is organized as 8,192 rows

by 512 columns by 16 bits. The MCP also incorporates

two 16-bit universal bus drivers for input control signals

and addresses.

ꢀ

Registered for enhanced performance of bus

speeds

•

66, 100, 125, 133** MHz

ꢀ

Package:

•

219 Plastic Ball Grid Array (PBGA), 32 x 25mm

ꢀ

Single 3.3V 0.3V power supply

Fully Synchronous; all signals registered on positive

edge of system clock cycle

Read and write accesses to the SDRAM are burst oriented;

accesses start at a selected location and continue for

a programmed number of locations in a programmed

sequence. Accesses begin with the registration of an

ACTIVE command, which is then followed by a READ or

WRITE command. The address bits registered coincident

with the ACTIVE command are used to select the bank

and row to be accessed (BA0, BA1 select the bank; A0-

12 select the row). The address bits registered coincident

with the READ or WRITE command are used to select the

starting column location for the burst access.

ꢀ

Internal pipelined operation; column address can be

changed every clock cycle

ꢀ

Internal banks for hiding row access/precharge

Programmable Burst length 1,2,4,8 or full page

8,192 refresh cycles

Commercial, Industrial and Military Temperature

Ranges

ꢀ

Organized as 16M x 64

The SDRAM provides for programmable READ or WRITE

burst lengths of 1, 2, 4 or 8 locations, or the full page, with

a burst terminate option.AnAUTO PRECHARGE function

may be enabled to provide a self-timed row precharge that

is initiated at the end of the burst sequence.

•

User conﬁgureable as 32M x 32

Weight: WEDPN16M64VR-XBX - 2.5 grams typical

BENEFITS

ꢀ

37% SPACE SAVINGS

The 1Gb SDRAM uses an internal pipelined architecture

to achieve high-speed operation. This architecture is

compatible with the 2n rule of prefetch architectures, but

it also allows the column address to be changed on every

clock cycle to achieve a high-speed, fully random access.

Precharging one bank while accessing one of the other

three banks will hide the precharge cycles and provide

seamless, high-speed, random-access operation.

17% I/O Reduction

Reduced part count

Reduced trace lengths for lower parasitic

capacitance

ꢀ

Glue-less connection to memory controller/PCI

Bridge

ꢀ

Suitable for hi-reliability applications

The 1Gb SDRAM is designed to operate in 3.3V, low-power

memory systems.An auto refresh mode is provided, along

with a power-saving, power-down mode.

Laminate interposer for optimum TCE match

Upgradeable to 32M x 64 density (contact factory

for information)

All inputs and outputs are LVTTLcompatible. SDRAMs offer

substantial advances in DRAM operating performance,

including the ability to synchronously burst data at a high

data rate with automatic column-address generation,

the ability to interleave between internal banks in order

to hide precharge time and the capability to randomly

change column addresses on each clock cycle during a

burst access.

* This data sheet describes a product that is Not Recommended for New Designs, refer

to WEDPN16M64VR-XB2X for new designs.

** Available in commercial and industrial temperatures only.

April 2004

Rev. 5

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

12 3 4 5 6 7...15

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与WEDPN16M64VR-66BC相关器件

型号	品牌	获取价格	描述	数据表
WEDPN16M64VR-66BI	MICROSEMI	获取价格	Synchronous DRAM Module, 16MX64, 7.5ns, CMOS, PBGA219, 32 X 25 MM, PLASTIC, BGA-219
WEDPN16M64VR-66BM	WEDC	获取价格	Synchronous DRAM Module, 16MX64, 7.5ns, CMOS, PBGA219, 32 X 25 MM, PLASTIC, BGA-219
WEDPN16M64VR-XB2X	WEDC	获取价格	16Mx64 REGISTERED SYNCHRONOUS DRAM
WEDPN16M64VR-XBX	ETC	获取价格	Registered SDRAM MCP
WEDPN16M64V-XB2X	WEDC	获取价格	16Mx64 Synchronous DRAM
WEDPN16M64V-XBX	ETC	获取价格	SDRAM MCP
WEDPN16M72V-100B2C	WEDC	获取价格	16Mx72 Synchronous DRAM
WEDPN16M72V-100B2I	WEDC	获取价格	16Mx72 Synchronous DRAM
WEDPN16M72V-100B2M	WEDC	获取价格	16Mx72 Synchronous DRAM
WEDPN16M72V-125B2C	WEDC	获取价格	16Mx72 Synchronous DRAM

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