Datasheet > WED3EG72M32S355JD3IGG

WED3EG72M32S355JD3IGG

更新时间： 2024-10-01 02:59:31

品牌	Logo	应用领域
WEDC		动态存储器双倍数据速率
页数	文件大小	规格书
12页	190K
描述
256MB - 32Mx72 DDR SDRAM UNBUFFERED

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WED3EG7232S-JD3

PRELIMINARY

256MB – 32Mx72 DDR SDRAM UNBUFFERED

FEATURES

DESCRIPTION

ꢀ

Double-data-rate architecture

The WED3EG7232S is a 32Mx72 Double Data Rate

SDRAM memory module based on 256Mb DDR SDRAM

components. The module consists of nine 32Mx8 DDR

SDRAMs in 66 pin TSOP packages mounted on a 184

pin FR4 substrate.

ꢀ

DDR200, DDR266, DDR333 amd DDR400

• JEDEC design speciﬁcations

ꢀ

Bi-directional data strobes (DQS)

Differential clock inputs (CK & CK#)

Programmable Read Latency 2, 2.5 (clock)

Programmable Burst Length (2, 4, 8)

Programmable Burst type (sequential & interleave)

Edge aligned data output, center aligned data input.

Auto and self refresh

Synchronous design allows precise cycle control with the

use of system clock. Data I/O transactions are possible on

both edges and Burst Lengths allow the same device to be

useful for a variety of high bandwidth, high performance

memory system applications.

* This product is under development, is not qualiﬁed or characterized and is subject to

change without notice.

Serial presence detect

Power supply:

• V_CC= V_CCQ= +2.5V ± 0.2V (100, 133 and

166MHz)

• V_CC= V_CCQ= +2.6V ± 0.1V (200MHz)

JEDEC 184 pin DIMM package

ꢀ

• JD3 PCB height: 30.48 (1.20") Max

NOTE: Consult factory for availability of:

• RoHS compliant products

• Vendor source control options

• Industrial temperature option

OPERATING FREQUENCIES

DDR400 @CL=3

DDR333 @CL=2.5

166MHz

DDR266 @CL=2

133MHz

DDR266 @CL=2.5

133MHz

DDR200 @CL=2

100MHz

Clock Speed

CL-t_RCD-t_RP

200MHz

3-3-3

2.5-3-3

2-2-2

2.5-3-3

2-2-2

June 2006

Rev. 6

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

12 3 4 5 6 7...12

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