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WED416S8030A10SI PDF预览

WED416S8030A10SI

更新时间: 2024-10-01 03:54:59
品牌 Logo 应用领域
WEDC 存储内存集成电路光电二极管动态存储器时钟
页数 文件大小 规格书
12页 164K
描述
2Mx16x 4 Banks Synchronous DRAM

WED416S8030A10SI 数据手册

 浏览型号WED416S8030A10SI的Datasheet PDF文件第2页浏览型号WED416S8030A10SI的Datasheet PDF文件第3页浏览型号WED416S8030A10SI的Datasheet PDF文件第4页浏览型号WED416S8030A10SI的Datasheet PDF文件第5页浏览型号WED416S8030A10SI的Datasheet PDF文件第6页浏览型号WED416S8030A10SI的Datasheet PDF文件第7页 
WED416S8030A-SI  
White Electronic Designs  
2Mx16x 4 Banks Synchronous DRAM  
FEATURES  
DESCRIPTION  
Single 3.3V power supply  
The WED416S8030AxxSI is 134,217,728 bits of  
synchronous high data rate DRAM organized as 4 x  
2,097, 152 words x 16 bits. Synchronous design allows  
precise cycle control with the use of system clock, I/O  
transactions are possible on every clock cycle. Range of  
operating frequencies, programmable burst lengths and  
programmable latencies allow the same device to be useful  
for a variety of high bandwidth, high performance memory  
system applications.  
Fully Synchronous to positive Clock Edge  
SDRAM CAS Latentency = 3 (100MHz), 2 (83MHz)  
Burst Operation  
• Sequential or Interleave  
• Burst length = programmable 1,2,4,8 or full page  
• Burst Read and Write  
• Multiple Burst Read and Single Write  
DATA Mask Control per byte  
Available in a 54 pin TSOP type II package the  
WED416S4030AxxSI is tested over the industrial temp  
range (-40°C to +85°C) providing a solution for rugged  
main memory applications.  
Auto Refresh (CBR) and Self Refresh  
• 4096 refresh cycles across 64ms  
Automatic and Controlled Precharge Commands  
Suspend Mode and Power Down Mode  
PIN CONFIGURATIONS  
PIN DESCRIPTION  
CLK  
Clock Input  
CKE  
Clock Enable  
VCC  
DQ0  
VCCQ  
DQ1  
DQ2  
VSSQ  
DQ3  
DQ4  
VCCQ  
DQ5  
DQ6  
VSSQ  
DQ7  
VCC  
1
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
VSS  
RAS#  
CAS#  
WE#  
Row Address Strobe  
Column Address Strobe  
Write Enable  
Chip Select  
Address Inputs  
Bank Select Address  
Data Input/Output  
Data Input/Output Mask  
Power (+3.3V 10ꢀ)  
Data Output Power  
Ground  
2
DQ15  
VSSQ  
DQ14  
DQ13  
VCCQ  
DQ12  
DQ11  
VSSQ  
DQ10  
DQ9  
VCCQ  
DQ8  
VSS  
3
4
5
CE#  
6
7
A0-A11  
BA0, BA1  
DQ0-DQ15  
L(U)DQM  
VCC  
VCCQ  
VSS  
VSSQ  
NC  
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
LDQM  
WE#  
CAS#  
RAS#  
CE#  
BA0  
NC/RFU  
UDQM  
CK  
Data Output Ground  
No Connection  
CKE  
NC  
A11  
BA1  
A9  
A10/AP  
A0  
A8  
A7  
A1  
A6  
A2  
A5  
A3  
A4  
VCC  
VSS  
White Electronic Designs Corp. reserves the right to change products or specifications without notice.  
October 2004  
Rev. 4  
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com  

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