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WED416S16030A7SI

更新时间: 2024-10-01 19:58:15
品牌 Logo 应用领域
WEDC 动态存储器光电二极管内存集成电路
页数 文件大小 规格书
26页 398K
描述
Synchronous DRAM, 16MX16, 5.4ns, CMOS, PDSO54, TSOP2-54

WED416S16030A7SI 数据手册

 浏览型号WED416S16030A7SI的Datasheet PDF文件第2页浏览型号WED416S16030A7SI的Datasheet PDF文件第3页浏览型号WED416S16030A7SI的Datasheet PDF文件第4页浏览型号WED416S16030A7SI的Datasheet PDF文件第5页浏览型号WED416S16030A7SI的Datasheet PDF文件第6页浏览型号WED416S16030A7SI的Datasheet PDF文件第7页 
WED416S16030A  
White Electronic Designs  
4M x 16 Bits x 4 Banks Synchronous DRAM  
FEATURES  
DESCRIPTION  
Single 3(3V power supply  
Fully Synchronous to positive Clock Edge  
Clock Frequency = 133, 125, and 100MHz  
SDRAM CAS Latency = 2  
Burst Operation  
The WED416S16030A is 268,435,456 bits of synchro-  
nous high data rate DRAM organized as 4 x 4,196,304  
words x 16 bits( Synchronous design allows precise  
cycle control with the use of system clock( I/O transac-  
tions are possible on every clock cycle( Range of oper-  
ating frequencies, programmable burst lengths and pro-  
grammable latencies allow the same device to be use-  
ful for a variety of high bandwidth, high performance  
memory system applications(  
•
•
•
•
Sequential or Interleave  
Burst length = programmable 1,2,4,8 or full page  
Burst Read and Write  
Available in a 54 pin TSOP type II package the  
WED416S16030A is tested over the industrial temp  
range ꢀ-40°C to +85°C) providing a solution for rugged  
main memory applications(  
Multiple Burst Read and Single Write  
DATA Mask Control per byte  
Auto Refresh ꢀCBR) and Self Refresh  
•
8192 refresh cycles across 64ms  
Automatic and Controlled Precharge Commands  
Suspend Mode and Power Down Mode  
Industrial Temperature Range  
FIGꢀ 1  
PIN DESCRIPTION  
PIN CONFIGURATION  
A0-12  
Address Inputs  
V
DQ  
DD  
1
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
V
SS  
DQ15  
SSQ  
0
2
BA0, BA1 Bank Select Addresses  
V
DDQ  
3
V
CE  
WE  
Chip Select  
DQ  
DQ  
1
2
4
DQ14  
DQ13  
5
Write Enable  
Clock Input  
V
SSQ  
6
VDDQ  
DQ  
DQ  
3
4
7
DQ12  
DQ11  
CLK  
8
V
DDQ  
9
V
SSQ  
DQ10  
DQ  
CKE  
DQ0-15  
Clock Enable  
Data Input/Output  
DQ  
DQ  
5
6
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
9
V
SSQ  
VDDQ  
L(U)DQM Data Input/Output Mask  
DQ  
V
7
DQ8  
DD  
VSS  
RAS  
CAS  
VDD  
Row Address Strobe  
Column Address Strobe  
Power (3*3V)  
LDQM  
WE  
CAS  
RAS  
CE  
BA  
BA  
10/AP  
NC/RFU  
UDQM  
CLK  
CKE  
A
A
A
A
A
A
A
A
V
12  
11  
9
8
7
6
5
4
SS  
VDDQ  
VSS  
Data Output Power  
Ground  
0
1
A
A
A
A
A
0
1
2
3
VSSQ  
NC  
Data Output Ground  
No Connection  
V
DD  
1
White Electronic Designs Corporation • (508) 366-5151 • wwwꢀwhiteedcꢀcom  
June 2002 Revꢀ 0  
ECO #15332  

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