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W83194R-81 PDF预览

W83194R-81

更新时间: 2024-02-05 05:56:17
品牌 Logo 应用领域
华邦 - WINBOND 晶体时钟发生器微控制器和处理器外围集成电路光电二极管
页数 文件大小 规格书
18页 230K
描述
100MHZ CLOCK FOR SIS CHIPSET

W83194R-81 技术参数

生命周期:Obsolete零件包装代码:SSOP
包装说明:SSOP, SSOP48,.4针数:48
Reach Compliance Code:compliant风险等级:5.8
JESD-30 代码:R-PDSO-G48端子数量:48
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装等效代码:SSOP48,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH电源:2.5,3.3 V
认证状态:Not Qualified子类别:Clock Generators
表面贴装:YES温度等级:COMMERCIAL
端子形式:GULL WING端子节距:0.635 mm
端子位置:DUALBase Number Matches:1

W83194R-81 数据手册

 浏览型号W83194R-81的Datasheet PDF文件第4页浏览型号W83194R-81的Datasheet PDF文件第5页浏览型号W83194R-81的Datasheet PDF文件第6页浏览型号W83194R-81的Datasheet PDF文件第8页浏览型号W83194R-81的Datasheet PDF文件第9页浏览型号W83194R-81的Datasheet PDF文件第10页 
W83194R-81  
PRELIMINARY  
8.0 FUNTION DESCRIPTION  
8.1 POWER MANAGEMENT FUNCTIONS  
All clocks can be individually enabled or disabled via the 2-wire control interface. On power up,  
external circuitry should allow 3 ms for the VCO to stabilize prior to enabling clock outputs to  
assure correct pulse widths. When MODE=0, pins 17, 18, 20 and 21 are inputs (PCI_STOP#),  
(CPU_STOP#), (SDRAM_STOP#), (PD#). when MODE=1, these functions are not available.  
A
particular clock could be enabled as both the 2-wire serial control interface and one of these pins  
indicate that it should be enabled.  
The W83194R-81 may be disabled in the low state according to the following table in order to reduce  
power consumption. All clocks are stopped in the low state, but maintain a valid high period on  
transitions from running to stop. The CPU and PCI clocks transform between running and stop by  
waiting for one positive edge on PCICLK_F followed by negative edge on the clock of interest, after  
which high levels of the output are either enabled or disabled.  
MODE PIN-POWER MANAGEMENT INPUT  
MODE(Pin2)  
0 (Input)  
Pin17  
Pin18  
Pin20  
Pin21  
PD#  
CPU_STOP#  
SDRAM11  
PCI_STOP#  
SDRAM10  
SDRAM_STOP#  
SDRAM9  
1 (Output)  
SDRAM8  
PD#  
CPU_STOP#  
PCI_STOP#  
SDRAM  
_STOP#  
PCI [0:4]  
SDRAM  
[0:12]  
CPU[1:2]  
XTAL &  
VCOs  
0
1
1
1
1
1
1
1
1
1
X
X
1
1
1
1
0
0
0
0
X
X
1
1
0
0
1
1
0
0
X
X
1
0
1
0
1
0
1
0
Low  
Low  
Low  
Running  
Running  
Running  
Running  
Running  
Low  
Low  
Running Running  
Running Running  
Running Running  
Running  
Running  
Running  
Running  
Running  
Running  
Running  
Running  
Running  
Low  
Low  
Running  
Low  
Running Running  
Running  
Low  
Low  
Running  
Low  
Low  
Low  
Low  
Low  
Publication Release Date: Dec. 1998  
Revision 0.20  
- 7 -  

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