Datasheet > W3EG72126MS133D3SF

W3EG72126MS133D3SF

更新时间： 2024-01-19 23:04:02

品牌	Logo	应用领域
WEDC		动态存储器双倍数据速率
页数	文件大小	规格书
15页	339K
描述
1GB-128Mx72 DDR SDRAM REGISTERED ECC w/PLL

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W3EG72126S-D3

-JD3

White Electronic Designs

-AJD3

PRELIMINARY*

1GB-128Mx72 DDR SDRAM REGISTERED ECC w/PLL

FEATURES

DESCRIPTION

ꢀ

Double-data-rate architecture

The W3EG72126S is a 128Mx72 Double Data Rate

SDRAM memory module based on 512Mb DDR SDRAM

components. The module consists of eighteen 128Mx4

DDR SDRAMs in 66 pin TSOP packages mounted on a

184 pin FR4 substrate.

ꢀ

DDR200, DDR266 and DDR333:

• JEDEC design speciﬁcations

ꢀ

Bi-directional data strobes (DQS)

Differential clock inputs (CK & CK#)

Programmable Read Latency 2,2.5 (clock)

Programmable Burst Length (2,4,8)

Programmable Burst type (sequential & interleave)

Edge aligned data output, center aligned data input.

Auto and self refresh

Synchronous design allows precise cycle control with the

use of system clock. Data I/O transactions are possible on

both edges and Burst Lengths allow the same device to be

useful for a variety of high bandwidth, high performance

memory system applications.

* This product is under development, is not qualiﬁed or characterized and is subject to

change without notice.

Serial presence detect

Power supply: V_CC= 2.5V 0.20V

JEDEC standard 184 pin DIMM package

• Package height options:

JD3: 30.48mm (1.20") and

AJD3: 28.70mm (1.13")

• Consult factory for availability of lead-free

products.

OPERATING FREQUENCIES

DDR333 @CL=2.5

166MHz

DDR266 @CL=2

133MHz

2-2-2

DDR266 @CL=2

133MHz

2-3-3

DDR266 @CL=2.5

133MHz

DDR200 @CL=2

100MHz

Clock Speed

CL-t_RCD-t_RP

2.5-3-3

2-2-2

November 2004

Rev. 3

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

12 3 4 5 6 7...15

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