W3EG6464S262JD3G

更新时间： 2024-01-22 18:08:43

品牌	Logo	应用领域
WEDC		动态存储器双倍数据速率
页数	文件大小	规格书
12页	293K
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数据手册

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W3EG6464S262JD3G 数据手册

W3EG6464S-JD3-D3

White Electronic Designs

PRELIMINARY*

512MB – 64Mx64 DDR SDRAM UNBUFFERED

FEATURES

DESCRIPTION

ꢀ

Double-data-rate architecture

The W3EG6464S is a 64Mx64 Double Data Rate

SDRAM memory module based on 512Mb DDR SDRAM

components. The module consists of eight 64Mx8 DDR

SDRAMs in 66 pin TSOP packages mounted on a 184

pin FR4 substrate.

ꢀ

DDR200 and DDR266

• JEDEC design speciﬁcation

Bi-directional data strobes (DQS)

Differential clock inputs (CK & CK#)

Programmable Read Latency 2,2.5 (clock)

Programmable Burst Length (2,4,8)

Programmable Burst type (sequential & interleave)

Edge aligned data output, center aligned data input.

Auto and self refresh

ꢀ

Synchronous design allows precise cycle control with the

use of system clock. Data I/O transactions are possible on

both edges and Burst Lengths allow the same device to be

useful for a variety of high bandwidth, high performance

memory system applications.

* This product is under development, is not qualiﬁed or characterized and is subject to

change without notice.

Serial presence detect

Power supply: V_CC: 2.5V 0.20V

JEDEC standard 184 pin DIMM package

• Package height option:

JD3: 30.48mm (1.20")

NOTE: Consult factory for availability of:

• Lead-Free Products

• Vendor source control options

• Industrial temperature options

OPERATING FREQUENCIES

DDR266 @CL=2

133MHz

DDR266 @CL=2.5

133MHz

DDR266 @CL=2

133MHz

DDR200 @CL=2

100MHz

Clock Speed

CL-t_RCD-t_RP

2-2-2

2.5-3-3

2-3-3

2-2-2

May 2005

Rev. 3

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

12 3 4 5 6 7...12

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