Datasheet > W3EG6464S-BD4

W3EG6464S-BD4

更新时间： 2024-01-14 09:29:28

品牌	Logo	应用领域
WEDC		动态存储器双倍数据速率
页数	文件大小	规格书
9页	100K
描述
512MB - 64Mx64 DDR SDRAM UNBUFFERED w/PLL

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中文翻译

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W3EG6464S-BD4 数据手册

W3EG6464S-AD4

-BD4

White Electronic Designs

PRELIMINARY*

512MB - 64Mx64 DDR SDRAM UNBUFFERED w/PLL

FEATURES

DESCRIPTION

The W3EG6464S is a 64Mx64 Double Data Rate

SDRAM memory module based on 512Mb DDR SDRAM

component. The module consists of eight 64Mx8 DDR

SDRAMs in 66 pin TSOP packages mounted on a 200

pin FR4 substrate.

ꢀ

Double-data-rate architecture

Speeds of 100MHz, 133MHz and 166MHz

Bi-directional data strobes (DQS)

Differential clock inputs (CK & CK#)

Programmable Read Latency 2,2.5 (clock)

Programmable Burst Length (2,4,8)

Programmable Burst type (sequential & interleave)

Edge aligned data output, center aligned data input

Auto and self refresh

Synchronous design allows precise cycle control with the

use of system clock. Data I/O transactions are possible on

both edges and Burst Lengths allow the same device to be

useful for a variety of high bandwidth, high performance

memory system applications.

Serial presence detect

* This product is under development, is not qualiﬁed or characterized and is subject to

change without notice.

Power supply: V_CC: 2.5V 0.2V

JEDEC standard 200 pin SO-DIMM package

•

Package height options:

AD4: 35.5 mm (1.38"),

BD4: 31.75 (1.25")

OPERATING FREQUENCIES

DDR333@CL=2.5

DDR266@CL=2

133MHz

DDR266@CL=2.5

133MHz

DDR200@CL=2

100MHz

Clock Speed

CL-t_RCD-t_RP

166MHz

2.5-3-3

2-2-2

2.5-3-3

2-2-2

March 2004

Rev. 1

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

12 3 4 5 6 7...9

中文翻译

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