PRELIMINARY
W209C
Frequency Generator for Integrated Core Logic
with 133-MHz FSB
Features
Table 1. Frequency Selections
FS4 FS3 FS2 FS1 FS0 CPU SDRAM 3V66 PCI APIC
SS
OFF
–0.6%
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
• Maximized EMI suppression using Cypress’s Spread
Spectrum technology
• Low jitter and tightly controlled clock skew
• Highly integrated device providing clocks required for
CPU, core logic, and SDRAM
• Two copies of CPU clock
• Nine copies of SDRAM clock
• Eight copies of PCI clock
• One copy of synchronous APIC clock
• Two copies of 66-MHz outputs
• Two copies of 48-MHz outputs
• One copy of selectable 24- or 48-MHz clock
• One copy of double strength 14.31818-MHz reference
clock
• Power-down control
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
75.3
95.0
113.0
95.0
75.3 37.6 18.8
63.3 31.6 15.8
86.0 43.0 21.5
75.3 37.6 18.8
129.0 129.0
150.0 113.0
150.0 150.0 100.0 50.0 25.0
110.0
110.0
73.0 36.6 18.3
93.3 46.7 23.3
72.0 36.0 18.0
68.3 34.1 17.0
70.0 35.0 17.5
92.0 46.0 23.0
70.0 35.0 17.5
140.0 140.0
144.0 108.0
68.3
102.5
105.0 105.0
138.0 138.0
140.0 105.0
66.8
100.2
66.8 33.4 16.7 ±0.45%
66.8 33.4 16.7 ±0.45%
89.1 44.4 22.2 ±0.45%
66.8 33.4 16.7 ±0.45%
100.2 100.2
133.6 133.6
133.6 100.2
157.3 118.0
160.0 120.0
146.6 110.0
• SMBus interface for turning off unused clocks
78.6 39.3 19.6
80.0 40.0 20.0
73.3 36.6 18.3
61.0 30.5 15.2
84.6 42.3 21.1
81.3 40.6 20.3
78.0 39.0 19.5
76.0 38.0 19.0
80.0 40.0 20.0
78.0 39.0 19.5
55.3 27.6 13.8
53.3 26.7 13.3
66.6 33.3 16.6
66.6 33.3 16.6
88.9 44.4 22.2
66.6 33.3 16.6
OFF
OFF
Key Specifications
OFF
122.0
91.5
–0.6%
OFF
CPU, SDRAM Outputs Cycle-to-Cycle Jitter: ............. 250 ps
127.0 127.0
122.0 122.0
APIC, 48-MHz, 3V66, PCI Outputs
Cycle-to-Cycle Jitter:................................................... 500 ps
–0.6%
OFF
117.0
114.0
80.0
117.0
114.0
120.0
117.0
CPU, 3V66 Output Skew: ........................................... 175 ps
SDRAM, APIC, 48-MHz Output Skew: ....................... 250 ps
PCI Output Skew: ....................................................... 500 ps
CPU to SDRAM Skew (@ 133 MHz) ....................... ± 0.5 ns
CPU to SDRAM Skew (@ 100 MHz)................. 4.5 to 5.5 ns
CPU to 3V66 Skew (@ 66 MHz)........................ 7.0 to 8.0 ns
3V66 to PCI Skew (3V66 lead).......................... 1.5 to 3.5 ns
PCI to APIC Skew..................................................... ± 0.5 ns
OFF
OFF
78.0
OFF
166.0 166.0
160.0 160.0
OFF
OFF
66.6
100.0
–0.6%
–0.6%
–0.6%
–0.6%
100.0 100.0
133.3 133.3
133.3 100.0
VDDQ3
Pin Configuration[1]
Block Diagram
REF2X/FS3*
X1
X2
XTAL
OSC
VDDQ2
APIC
VDDQ2
CPU0
CPU1
GND
VDDQ3
SDRAM0
SDRAM1
SDRAM2
GND
SDRAM3
SDRAM4
SDRAM5
VDDQ3
SDRAM6
SDRAM7
DCLK
GND
PWRDWN#
SCLK
REF2x/FS3*
VDDQ3
X1
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
PLL REF FREQ
2
VDDQ2
CPU0:1
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
X2
Divider,
Delay,
and
Phase
Control
Logic
GND
2
SDATA
SCLK
SMBus
Logic
VDDQ3
3V66_0
3V66_1
GND
FS0*/PCI0
FS1*/PCI1
FS2*/PCI2
GND
PCI3
PCI4
VDDQ3
PCI5
APIC
(FS0:4*)
VDDQ3
3V66_0:1
2
FS0*/PCI0
PLL 1
FS1*/PCI1
FS2*/PCI2
PCI3:7
PCI6
PCI7
GND
5
8
SDRAM0:7
DCLK
^
PWRDWN#
48MHz_0
FS4*/48MHz_1
SI0/24_48#MHz*
VDDQ3
VDDQ3
GND
SDATA
VDDQ3
48MHz_0
Note:
FS4*/48MHz_1
PLL2
1. Internal pull-down or pull-up resistors present on inputs marked with
* or ^ respectively. Design should not rely solely on internal pull-up
or pull-down resistor to set I/O pins HIGH or LOW respectively.
SI0/24_48#MHz*
/2
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-07171 Rev. *A
Revised December 15, 2002
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