Datasheet > W152-11X

W152-11X

更新时间： 2024-02-27 01:06:22

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		驱动光电二极管逻辑集成电路
页数	文件大小	规格书
8页	145K
描述
PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 4.40 MM, TSSOP-16

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W152-11X 技术参数

是否无铅：	不含铅	生命周期：	Active
零件包装代码：	TSSOP	包装说明：	TSSOP,
针数：	16	Reach Compliance Code：	unknown
风险等级：	5.7	输入调节：	MUX
JESD-30 代码：	R-PDSO-G16	JESD-609代码：	e1
长度：	5 mm	逻辑集成电路类型：	PLL BASED CLOCK DRIVER
湿度敏感等级：	1	功能数量：	1
反相输出次数：		端子数量：	16
实输出次数：	8	最高工作温度：	70 °C
最低工作温度：		输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	TSSOP
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：	260	认证状态：	COMMERCIAL
Same Edge Skew-Max（tskwd）：	0.215 ns	座面最大高度：	1.2 mm
最大供电电压 (Vsup)：	3.63 V	最小供电电压 (Vsup)：	2.97 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
温度等级：	COMMERCIAL	端子面层：	TIN SILVER COPPER
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	4.4 mm	最小 fmax：	140 MHz
Base Number Matches：	1

W152-11X 数据手册

W152

Pin Definitions

Type

Pin Name

Pin No.

Pin Description

REF

Reference Input: The output signals QA0:3 through QB0:3 will be synchronized to

this signal unless the device is programmed to bypass the PLL.

FBIN

Feedback Input: When programmed to zero delay buffer mode, this input must be

fed by one of the outputs (QA0:3 or QB0:3) to ensure proper functionality. If the trace

between FBIN and the output pin being used for feedback is equal in length to the

traces between the outputs and the signal destinations, then the signals received at

the destinations will be synchronized to the REF signal input.

QA0:3

QB0:3

VDD

2, 3, 14, 15

6, 7, 10, 11

4, 13

Outputs from Bank A: The frequency of the signals provided by these pins is deter-

mined by the feedback signal connected to FBIN, and the specific W152 option being

used. See Table 2.

Outputs from Bank B: The frequency of the signals provided by these pins is deter-

mined by the feedback signal connected to FBIN, and the specific W152 option being

used. See Table 2.

Power Connections: Connect to 3.3V. Use ferrite beads to help reduce noise for

optimal jitter performance.

GND

5, 12

9, 8

Ground Connections: Connect all grounds to the common system ground plane.

SEL0:1

Function Select Inputs: Tie to V_DD(HIGH, 1) or GND (LOW, 0) as desired per

Table 2.

Overview

Functional Description

The W152 products are eight-output zero delay buffers. A

Phase-Locked Loop (PLL) is used to take a time-varying signal

and provide eight copies of that same signal out. The external

feedback to the PLL provides outputs in phase with the refer-

ence inputs.

Logic inputs provide the user the ability to turn off one or both

banks of clocks when not in use, as described in Table 2. Dis-

abling a bank of unused outputs will reduce jitter and power

consumption, and will also reduce the amount of EMI gener-

ated by the W152.

Internal dividers exist in some options allowing the user to get

a simple multiple (/2, x2, x4) of the reference input, for details

see Table 1. Because the outputs are separated into two

banks, it is possible to provide some combination of these mul-

tiples at the same time.

These same inputs allow the user to bypass the PLL entirely

if so desired. When this is done, the device no longer acts as

a zero delay buffer, it simply reverts to a standard eight-output

clock driver.

The W152 PLL enters an auto power-down mode when there

are no rising edges on the REF input. In this mode, all outputs

are three-stated and the PLL is turned off.

Spread Aware

Many systems being designed now utilize a technology called

Spread Spectrum Frequency Timing Generation. Cypress has

been one of the pioneers of SSFTG development, and we de-

signed this product so as not to filter off the Spread Spectrum

feature of the Reference input, assuming it exists. When a

zero delay buffer is not designed to pass the SS feature

through, the result is a significant amount of tracking skew

which may cause problems in systems requiring synchroniza-

tion.

Table 2. Input Logic

SEL1 SEL0

QA0:3

QB0:3

PLL

Three-State Three-State

Shutdown

Active

Three-State Active, Utilized

Active

Shutdown,

Bypassed

Active

Active, Utilized

For more details on Spread Spectrum timing technology,

please see the Cypress application note titled, “EMI Suppres-

sion Techniques with Spread Spectrum Frequency Timing

Generator (SSFTG) ICs.”

Document #: 38-07148 Rev. **

Page 2 of 8

123 4 5 6 7 8

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W152-11XT	CYPRESS	PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), PDSO16, 4.40 MM, TSSOP-16	获取价格
W152-12G	ETC	EIGHT DISTRIBUTED-OUTPUT CLOCK DRIVER\|CMOS\|SOP\|16PIN\|PLASTIC	获取价格
W152-12X	ETC	Eight Distributed-Output Clock Driver	获取价格
W152-12XT	CYPRESS	PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), PDSO16, 4.40 MM, TSSOP-16	获取价格
W152-1G	ETC	EIGHT DISTRIBUTED-OUTPUT CLOCK DRIVER\|CMOS\|SOP\|16PIN\|PLASTIC	获取价格
W152-1GT	CYPRESS	PLL Based Clock Driver, W152 Series, 8 True Output(s), 0 Inverted Output(s), PDSO16, 0.150	获取价格

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