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W152-1X PDF预览

W152-1X

更新时间: 2024-11-05 20:12:31
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
8页 145K
描述
PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 4.40 MM, TSSOP-16

W152-1X 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP, TSSOP16,.25针数:16
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.7输入调节:MUX
JESD-30 代码:R-PDSO-G16JESD-609代码:e3
长度:5 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
湿度敏感等级:3功能数量:1
反相输出次数:端子数量:16
实输出次数:8最高工作温度:70 °C
最低工作温度:输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP16,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
电源:3.3 V认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.215 ns座面最大高度:1.2 mm
子类别:Clock Drivers最大供电电压 (Vsup):3.63 V
最小供电电压 (Vsup):2.97 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:20
宽度:4.4 mm最小 fmax:140 MHz
Base Number Matches:1

W152-1X 数据手册

 浏览型号W152-1X的Datasheet PDF文件第2页浏览型号W152-1X的Datasheet PDF文件第3页浏览型号W152-1X的Datasheet PDF文件第4页浏览型号W152-1X的Datasheet PDF文件第5页浏览型号W152-1X的Datasheet PDF文件第6页浏览型号W152-1X的Datasheet PDF文件第7页 
W152  
Spread Aware™, Eight Output Zero Delay Buffer  
Output to Output Skew: Between Banks.....................215 ps  
Features  
Output to Output Skew: Within Banks  
• Spread Aware™—designed to work with SSFTG  
reference signals  
• Two banks of four outputs each  
• Configuration options to halve, double, or quadruple  
the reference frequency refer to Table 1 to determine  
the specific option which meets your multiplication  
needs  
(Refer to Figure 4)...................................................100 ps  
Total Timing Budget Impact:........................................555 ps  
Max. Phase Error Variation:.......................................±225 ps  
Tracking Skew:..........................................................±130 ps  
Table 1. Configuration Options  
• Outputs may be three-stated  
Device  
W152-1/11[1]  
W152-2/12[2]  
W152-2/12[2]  
W152-3  
Feedback Signal  
QA0:3 or QB0:3  
QA0:3  
QA0:3  
REFx1  
REFx1  
REFx2  
REFx2  
REFx4  
REFx2  
QB0:3  
REFx1  
REF/2  
REFx1  
REFx1  
REFx2  
REFx2  
• Available in 16-pin SOIC package  
• Extra strength output drive available (-11/-12 versions)  
• Contact factory for availability information on 16-pin  
TSSOP  
QB0:3  
Key Specifications  
QA0:3  
Operating Voltage: ............................................... 3.3V±10%  
Operating Range: ................... 15 MHz < fOUTQA < 140 MHz  
Cycle-to-Cycle Jitter: (Refer to Figure 3) .................... 225 ps  
W152-3  
QB0:3  
W152-4  
QA0:3 or QB0:3  
Notes:  
1. W152-11 has stronger output drive than the W152-1.  
2. W152-12 has stronger output drive than the W152-2.  
Cycle-to-Cycle Jitter: Frequency Range  
25 to140 MHz ......................................................... 125 ps  
Block Diagram  
Pin Configuration  
(present on the -3 and -4 only)  
FBIN  
REF  
÷2  
PLL  
REF  
QA0  
QA1  
VDD  
GND  
QB0  
QB1  
SEL1  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
FBIN  
QA3  
QA2  
VDD  
GND  
QB3  
QB2  
SEL0  
MUX  
QA0  
QA1  
QA2  
SEL0  
SEL1  
QA3  
÷2  
QB0  
QB1  
QB2  
QB3  
(present on the -2, -12, and -3 only)  
Spread Aware is a trademark of Cypress Semiconductor Corporation.  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
Document #: 38-07148 Rev. **  
Revised September 24, 2001  

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