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W150H PDF预览

W150H

更新时间: 2024-02-02 10:13:54
品牌 Logo 应用领域
SPECTRALINEAR 晶体外围集成电路光电二极管时钟
页数 文件大小 规格书
14页 231K
描述
440BX AGPset Spread Spectrum Frequency Synthesizer

W150H 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:ActiveReach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8541.40.20.00
风险等级:5.33其他特性:IC COMPATIBLE, HIGH RELIABILITY
颜色:HIGH EFFICIENCY RED/YELLOW颜色@波长:Orange/Yellow
配置:COMMON CATHODE, 2 ELEMENTS最大正向电流:0.03 A
最大正向电压:2.5 V透镜类型:DIFFUSED WHITE
标称发光强度:60.0/40.0 mcd安装特点:RADIAL MOUNT
功能数量:1端子数量:3
最高工作温度:85 °C最低工作温度:-40 °C
光电设备类型:DUAL COLOR LED总高度:6.22 mm
包装方法:BULK峰值波长:627/590 nm
最大反向电压:5 V形状:ROUND
尺寸:5 mm子类别:Visible LEDs
表面贴装:NOT代码:T-1 3/4
端子节距:1.27 mm视角:60 deg
Base Number Matches:1

W150H 数据手册

 浏览型号W150H的Datasheet PDF文件第2页浏览型号W150H的Datasheet PDF文件第3页浏览型号W150H的Datasheet PDF文件第4页浏览型号W150H的Datasheet PDF文件第6页浏览型号W150H的Datasheet PDF文件第7页浏览型号W150H的Datasheet PDF文件第8页 
W150  
MAX  
MIN  
Figure 4. Typical Modulation Profile  
outputs of the chipset. If needed, clock device register  
changes are normally made upon system initialization. The  
interface can also be used during system operation for power  
management functions. Table 3 summarizes the control  
functions of the serial data interface.  
Serial Data Interface  
The W150 features a two-pin, serial data interface that can be  
used to configure internal register settings that control  
particular device functions. Upon power-up, the W150  
initializes with default register settings, therefore the use of this  
serial data interface is optional. The serial interface is  
write-only (to the clock chip) and is the dedicated function of  
device pins SDATA and SCLOCK. In motherboard applica-  
tions, SDATA and SCLOCK are typically driven by two logic  
Operation  
Data is written to the W150 in eleven bytes of eight bits each.  
Bytes are written in the order shown in Table 4.  
Table 3. Serial Data Interface Control Functions Summary  
Control Function  
Description  
Common Application  
Clock Output Disable Any individual clock output(s) can be disabled.  
Disabled outputs are actively held LOW.  
Unused outputs are disabled to reduce EMI and  
system power. Examples are clock outputs to  
unused PCI slots.  
CPU Clock  
Provides CPU/PCI frequency selections through  
For alternate microprocessors and power  
management options. Smooth frequency transition  
allowsCPUfrequencychangeundernormalsystem  
operation.  
Frequency Selection software. Frequency is changed in a smooth and  
controlled fashion.  
Spread Spectrum  
Enabling  
Enables or disables spread spectrum clocking.  
Puts clock output into a high-impedance state.  
For EMI reduction.  
Output Three-state  
Test Mode  
Production PCB testing.  
Production PCB testing.  
All clock outputs toggle in relation to X1 input,  
internal PLL is bypassed. Refer to Table 5.  
(Reserved)  
Reserved function for future device revision or  
production device testing.  
No user application. Register bit must be written as  
0.  
Table 4. Byte Writing Sequence  
Byte  
Sequence Byte Name Bit Sequence  
Byte Description  
1
2
3
Slave Address 11010010  
Commands the W150 to accept the bits in Data Bytes 0–7 for internal register  
configuration. Since other devices may exist on the same common serial data bus,  
it is necessary to have a specific slave address for each potential receiver. The  
slave receiver address for the W150 is 11010010. Register setting will not be made  
if the Slave Address is not correct (or is for an alternate slave receiver).  
Command  
Code  
Don’t Care  
Don’t Care  
Unused by the W150, therefore bit values are ignored (“Don’t Care”). This byte  
must be included in the data write sequence to maintain proper byte allocation. The  
Command Code Byte is part of the standard serial communication protocol and  
may be used when writing to another addressed slave receiver on the serial data  
bus.  
Byte Count  
Unused by the W150, therefore bit values are ignored (“Don’t Care”). This byte  
must be included in the data write sequence to maintain proper byte allocation. The  
Byte Count Byte is part of the standard serial communication protocol and may be  
used when writing to another addressed slave receiver on the serial data bus.  
Rev 1.0,November 24, 2006  
Page 5 of 14  

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