Datasheet > W150H

W150H

更新时间： 2024-01-20 16:59:22

品牌	Logo	应用领域
SPECTRALINEAR		晶体外围集成电路光电二极管时钟
页数	文件大小	规格书
14页	231K
描述
440BX AGPset Spread Spectrum Frequency Synthesizer

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W150H 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	Reach Compliance Code：	compliant
ECCN代码：	EAR99	HTS代码：	8541.40.20.00
风险等级：	5.33	其他特性：	IC COMPATIBLE, HIGH RELIABILITY
颜色：	HIGH EFFICIENCY RED/YELLOW	颜色@波长：	Orange/Yellow
配置：	COMMON CATHODE, 2 ELEMENTS	最大正向电流：	0.03 A
最大正向电压：	2.5 V	透镜类型：	DIFFUSED WHITE
标称发光强度：	60.0/40.0 mcd	安装特点：	RADIAL MOUNT
功能数量：	1	端子数量：	3
最高工作温度：	85 °C	最低工作温度：	-40 °C
光电设备类型：	DUAL COLOR LED	总高度：	6.22 mm
包装方法：	BULK	峰值波长：	627/590 nm
最大反向电压：	5 V	形状：	ROUND
尺寸：	5 mm	子类别：	Visible LEDs
表面贴装：	NO	T代码：	T-1 3/4
端子节距：	1.27 mm	视角：	60 deg
Base Number Matches：	1

W150H 数据手册

W150

Pin Definitions (continued)

Pin No. Type

Pin Name

VDDQ2

Pin Description

50, 56

Power Connection: Power supply for IOAPIC and CPU output buffers. Connect to 2.5V or

3.3V.

GND

4, 10, 23,

26, 34,

42, 48, 53

Ground Connections: Connect all ground pins to the common system ground plane.

resistor on the l/O pins to pull the pins and their associated

capacitive clock load to either a logic HIGH or LOW state. At

Overview

The W150 was designed as a single-chip alternative to the

standard two-chip Intel 440BX AGPset clock solution. It

provides sufficient outputs to support most single-processor,

four SDRAM DIMM designs.

the end of the 2-ms period, the established logic “0” or “1”

condition of the l/O pin is latched. Next the output buffer is

enabled, converting the l/O pins into operating clock outputs.

The 2-ms timer starts when V_DDreaches 2.0V. The input bits

can only be reset by turning V_DDoff and then back on again.

Functional Description

It should be noted that the strapping resistors have no signif-

icant effect on clock output signal integrity. The drive

impedance of clock output (< 40:, nominal) is minimally

affected by the 10-k: strap to ground or V_DD. As with the

series termination resistor, the output strapping resistor should

be placed as close to the l/O pin as possible in order to keep

the interconnecting trace short. The trace from the resistor to

ground or V_DDshould be kept less than two inches in length

to minimize system noise coupling during input logic sampling.

I/O Pin Operation

Pins 2, 8, 9, 29, and 30 are dual-purpose l/O pins. Upon

power-up these pins act as logic inputs, allowing the determi-

nation of assigned device functions. A short time after

power-up, the logic state of each pin is latched and the pins

become clock outputs. This feature reduces device pin count

by combining clock outputs with input select pins.

An external 10-k: “strapping” resistor is connected between

the l/O pin and ground or V_DD. Connection to ground sets a

latch to “0,” connection to V_DDsets a latch to “1.” Figure 1 and

Figure 2 show two suggested methods for strapping resistor

connections.

When the clock outputs are enabled following the 2-ms input

period, the corresponding specified output frequency is

delivered on the pins, assuming that V_DDhas stabilized. If V_DD

has not yet reached full value, output frequency initially may

be below target but will increase to target once V_DDvoltage

has stabilized. In either case, a short output clock cycle may

be produced from the CPU clock outputs when the outputs are

enabled.

Upon W150 power-up, the first 2 ms of operation are used for

input logic selection. During this period, the five I/O pins (2, 8,

9, 29, 30) are three-stated, allowing the output strapping

Output Strapping Resistor

Series Termination Resistor

10 k:

(Load Option 1)

Clock Load

W150

Output

Buffer

Power-on

Reset

Timer

Hold

Output

Low

Output Three-state

10 k

(Load Option 0)

Data

Latch

Figure 1. Input Logic Selection Through Resistor Load Option

Rev 1.0,November 24, 2006

Page 3 of 14

1 234 5 6 7...14

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W150LVS/EGW	KINGBRIGHT	Dual Color LED, High Efficiency Red/green, Diffused White, T-1 3/4, 5mm,	获取价格
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