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W134H

更新时间: 2024-02-03 17:44:36
品牌 Logo 应用领域
芯科 - SILICON 光电二极管
页数 文件大小 规格书
11页 112K
描述
Direct Rambus™ Clock Generator

W134H 技术参数

生命周期:Transferred零件包装代码:SOIC
包装说明:,针数:24
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.48
JESD-30 代码:R-PDSO-G24端子数量:24
封装主体材料:PLASTIC/EPOXY封装形状:RECTANGULAR
封装形式:SMALL OUTLINE认证状态:Not Qualified
表面贴装:YES技术:CMOS
端子形式:GULL WING端子位置:DUAL
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, PROCESSOR SPECIFICBase Number Matches:1

W134H 数据手册

 浏览型号W134H的Datasheet PDF文件第5页浏览型号W134H的Datasheet PDF文件第6页浏览型号W134H的Datasheet PDF文件第7页浏览型号W134H的Datasheet PDF文件第8页浏览型号W134H的Datasheet PDF文件第10页浏览型号W134H的Datasheet PDF文件第11页 
W134  
Device Characteristics  
Parameter  
Description  
Min.  
Max.  
3.75  
60  
Unit  
ns  
ps  
tCYCLE  
tJ  
Clock Cycle Time  
Cycle-to-Cycle Jitter at Clk/ClkB[9]  
2.5  
Total Jitter over 2, 3, or 4 Clock Cycles[9]  
266-MHz Cycle-to-Cycle Jitter[10]  
266-MHz Total Jitter over 2, 3, or 4 Clock Cycles[10]  
100  
100  
160  
ps  
ps  
ps  
tSTEP  
Phase Aligner Phase Step Size (at Clk/ClkB)  
1
ps  
tERR,PD  
Phase Detector Phase Error for Distributed Loop Measured at  
PclkM-SynclkN (rising edges) (does not include clock jitter)  
–100  
100  
ps  
tERR,SSC  
VX,STOP  
VX  
PLL Output Phase Error when Tracking SSC  
Output Voltage during Clk Stop (StopB=0)  
Differential Output Crossing-Point Voltage  
Output Voltage Swing (p-p single-ended)[11]  
Output High Voltage  
–100  
1.1  
1.3  
0.4  
100  
2.0  
1.8  
0.6  
2.0  
ps  
V
V
VCOS  
VOH  
V
V
V
VOL  
Output Low voltage  
1.0  
12  
rOUT  
Output Dynamic Resistance (at pins)[12]  
Output Current during Hi-Z (S0 = 0, S1 = 1)  
Output Current during Clk Stop (StopB = 0)  
Output Duty Cycle over 10,000 Cycles  
Output Cycle-to-Cycle Duty Cycle Error  
Output Rise and Fall Times (measured at 20%–80% of output voltage)  
50  
IOZ  
50  
A  
IOZ,STOP  
DC  
tDC,ERR  
tR,tF  
500  
60  
A  
40  
%tCYCLE  
ps  
50  
250  
500  
100  
ps  
tCR,CF  
Difference between Output Rise and Fall Times on the Same Pin of a  
Single Device (20%–80%)  
ps  
Notes:  
9. Output Jitter spec measured at t  
= 2.5 ns.  
CYCLE  
10. Output Jitter Spec measured at t  
= 3.75 ns.  
CYCLE  
11. V  
= V –V  
COS  
OH OL.  
12. r  
= DV / D I . This is defined at the output pins.  
OUT  
O O  
........................Document #: 38-07426 Rev. *C Page 9 of 11  

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