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W134H

更新时间： 2024-01-23 16:08:47
品牌 Logo 应用领域
芯科 - SILICON 光电二极管
页数 文件大小 规格书
11页 112K
描述
Direct Rambus™ Clock Generator

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W134H 技术参数

生命周期：Transferred零件包装代码：SOIC
包装说明：,针数：24
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.48
JESD-30 代码：R-PDSO-G24端子数量：24
封装主体材料：PLASTIC/EPOXY封装形状：RECTANGULAR
封装形式：SMALL OUTLINE认证状态：Not Qualified
表面贴装：YES技术：CMOS
端子形式：GULL WING端子位置：DUAL
uPs/uCs/外围集成电路类型：CLOCK GENERATOR, PROCESSOR SPECIFICBase Number Matches：1

W134H 数据手册

 浏览型号W134H的Datasheet PDF文件第5页浏览型号W134H的Datasheet PDF文件第6页浏览型号W134H的Datasheet PDF文件第7页浏览型号W134H的Datasheet PDF文件第9页浏览型号W134H的Datasheet PDF文件第10页浏览型号W134H的Datasheet PDF文件第11页 
W134  
Absolute Maximum Conditions[1]  
Parameter  
Description  
Min.  
–0.5  
–0.5  
Max.  
4.0  
Unit  
V
VDD, ABS  
VI, ABS  
Max. voltage on VDD with respect to ground  
Max. voltage on any pin with respect ground  
VDD + 0.5  
V
External Component Values[2]  
Parameter  
Description  
Min.  
Max.  
±5%  
Unit  
RS  
Serial Resistor  
39  
RP  
Parallel Resistor  
51  
±5%  
CF  
Edge Rate Filter Capacitor  
AC Ground Capacitor  
4–15[3]  
±10%  
0.1 F  
pF  
CMID  
470 pF  
±20%  
Operating Conditions[4]  
Parameter  
Description  
Min.  
3.135  
0
Max.  
3.465  
70  
Unit  
VDD  
Supply Voltage  
V
°C  
TA  
Ambient Operating Temperature  
tCYCLE,IN  
tJ,IN  
Refclk Input Cycle Time  
Input Cycle-to-Cycle Jitter[5]  
10  
–
40  
ns  
250  
60  
ps  
DCIN  
FMIN  
Input Duty Cycle over 10,000 Cycles  
Input Frequency of Modulation  
40  
30  
–
%tCYCLE  
kHz  
33  
[6]  
PMIN  
Modulation Index for Triangular Modulation  
Modulation Index for Non-Triangular Modulation  
Phase Detector Input Cycle Time at PclkM & SynclkN  
Initial Phase error at Phase Detector Inputs  
Phase Detector Input Duty Cycle over 10,000 Cycles  
0.6  
0.5[8]  
100  
0.5  
75  
%
–
%
tCYCLE,PD  
tERR,INIT  
DCIN,PD  
tI,SR  
30  
–0.5  
25  
1
ns  
tCYCLE,PD  
tCYCLE,PD  
V/ns  
Input Slew Rate (measured at 20%-80% of input voltage) for PclkM,  
SynclkN, and Refclk  
4
CIN,PD  
Input Capacitance at PclkM, SynclkN, and Refclk[7]  
Input Capacitance matching at PclkM and SynclkN[7]  
–
–
–
7
pF  
pF  
pF  
DCIN,PD  
CIN,CMOS  
0.5  
10  
Input Capacitance at CMOS pins (excluding PclkM, SynclkN, and  
Refclk)[7]  
VIL  
Input (CMOS) Signal Low Voltage  
Input (CMOS) Signal High Voltage  
Refclk input Low Voltage  
–
0.7  
–
0.3  
–
VDD  
VDD  
VDDIR  
VDDIR  
VDDIPD  
VDDIPD  
V
VIH  
VIL,R  
VIH,R  
VIL,PD  
VIH,PD  
VDDIR  
VDDIPD  
0.3  
–
Refclk input High Voltage  
0.7  
–
Input Signal Low Voltage for PD Inputs and StopB  
Input Signal High Voltage for PD Inputs and StopB  
Input Supply Reference for Refclk  
Input Supply Reference for PD Inputs  
0.3  
–
0.7  
1.235  
1.235  
3.465  
2.625  
V
Notes:  
1. Represents stress ratings only, and functional operation at the maximums is not guaranteed.  
2. Gives the nominal values of the external components and their maximum acceptable tolerance, assuming Z = 28.  
CH  
3. Do not populate C . Leave pads for future use.  
F
4. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.  
5. Refclk jitter measured at V (nom)/2.  
DDIR  
6. If input modulation is used: input modulation is allowed but not required.  
7. Capacitance measured at Freq=1 MHz, DC bias = 0.9V and V < 100 mV.  
AC  
8. The amount of allowed spreading for any non-triangular modulation is determined by the induced downstream tracking skew, which cannot exceed the skew  
generated by the specified 0.6% triangular modulation. Typically, the amount of allowed non-triangular modulation is about 0.5%.  
........................Document #: 38-07426 Rev. *C Page 8 of 11  
1...567891011

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