Datasheet > W132-09BXT

W132-09BXT

更新时间： 2024-01-24 20:09:14

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		驱动光电二极管逻辑集成电路
页数	文件大小	规格书
7页	203K
描述
PLL Based Clock Driver, 132 Series, 9 True Output(s), 0 Inverted Output(s), PDSO24, MO-153AE, TSSOP-24

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W132-09BXT 技术参数

生命周期：	Obsolete	零件包装代码：	TSSOP
包装说明：	TSSOP,	针数：	24
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.75	系列：	132
输入调节：	STANDARD	JESD-30 代码：	R-PDSO-G24
长度：	7.8 mm	逻辑集成电路类型：	PLL BASED CLOCK DRIVER
功能数量：	1	反相输出次数：
端子数量：	24	实输出次数：	9
最高工作温度：	70 °C	最低工作温度：
输出特性：	SERIES-RESISTOR	封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	认证状态：	Not Qualified
Same Edge Skew-Max（tskwd）：	0.1 ns	座面最大高度：	1.1 mm
最大供电电压 (Vsup)：	3.63 V	最小供电电压 (Vsup)：	2.97 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
温度等级：	COMMERCIAL	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	DUAL
宽度：	4.4 mm	最小 fmax：	140 MHz
Base Number Matches：	1

W132-09BXT 数据手册

W132

Pin Definitions

Pin No.

(-10B)

Name

CLK

(-09B)

Type

Pin Description

Reference Input: Output signals Q0:9 will be synchronized to this signal.

FBIN

Feedback Input: This input must be fed by one of the outputs (typically FBOUT)

to ensure proper functionality. If the trace between FBIN and FBOUT is equal in

length to the traces between the outputs and the signal destinations, then the

signals received at the destinations will be synchronized to the CLK signal input.

Q0:8

3, 4, 5, 8,

9, 16, 17,

20, 21

3, 4, 5, 8,

9, 15, 16,

17, 20

Integrated Series Resistor Outputs: The frequency and phase of the signals

provided by these pins will be equal to the reference signal if properly laid out.

Each output has a 25Ω series damping resistor integrated.

Integrated Series Resistor Output: The frequency and phase of the signal

provided by this pin will be equal to the reference signal if properly laid out. This

output has a 25Ω series damping resistor integrated.

Feedback Output: This output has a 25Ω series resistor integrated on chip.

Typically it is connected directly to the FBIN input with a trace equal in length to

the traces between outputs Q0:9 and the destination points of these output

signals.

n/a

FBOUT

AVDD

2, 10, 15,

2, 10, 14,

Analog Power Connection: Connect to 3.3V. Use ferrite beads to help reduce

noise for optimal jitter performance.

AGND

VDD

Analog Ground Connection: Connect to common system ground plane.

Power Connections: Connect to 3.3V. Use ferrite beads to help reduce noise

for optimal jitter performance.

GND

6, 7, 18,

n/a

6, 7, 18,

Ground Connections: Connect to common system ground plane.

n/a

Output Enable Input: Tie to V_DD(HIGH, 1) for normal operation. when brought

to GND (LOW, 0) all outputs are disabled to a LOW state.

OE0:4

OE5:8

Output Enable Input: Tie to V_DD(HIGH, 1) for normal operation. when brought

to GND (LOW, 0) outputs Q0:4 are disabled to a LOW state.

Output Enable Input: Tie to V_DD(HIGH, 1) for normal operation. when brought

to GND (LOW, 0) outputs Q5:8 are disabled to a LOW state.

on the DIMM. The W132 takes in the signal from the mother-

board and buffers out clock signals with enough drive to sup-

Overview

The W132 is a PLL-based clock driver designed for use in dual

inline memory modules. The clock driver has output frequen-

cies of up to 133 MHz and output to output skews of less than

250 ps. The W132 provides minimum cycle-to-cycle and long

term jitter, which is of significant importance to meet the tight

input-to-input skew budget in DIMM applications.

The current generation of 256 and 512 megabyte memory

modules needs to support 100-MHz clocking speeds. Espe-

cially for cards configured in 16x4 or 8x8 format, the clock

signal provided from the motherboard is generally not strong

enough to meet all the requirements of the memory and logic

port all the DIMM board clocking needs. The W132 is also

designed to meet the needs of new PC133 SDRAM designs,

operating to 133 MHz.

The W132 was specifically designed to accept SSFTG signals

currently being used in motherboard designs to reduce EMI.

Zero delay buffers which are not designed to pass this feature

through may cause skewing failures.

Output enable pins allow for shutdown of output when they are

not being used. This reduces EMI and power consumption.

Document #: 38-07216 Rev. OBS

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