VSC8211
Datasheet
11
Twisted Pair Interface ................................................................................................................................................... 43
11.1 Twisted Pair Autonegotiation (IEEE802.3 Clause 28) ........................................................................ 43
11.2 Twisted Pair Auto MDI/MDI-X Function .............................................................................................. 44
11.3 Auto MDI/MDI-X in Forced 10/100 Link Speeds ................................................................................. 44
11.4 Twisted Pair Link Speed Downshift .................................................................................................... 45
11.5 100Mbps Fiber Support Over Copper Media Interface ....................................................................... 45
11.5.1
Register Settings ....................................................................................................................................45
12
13
Transformerless Operation for PICMG 2.16 and 3.0 IP-based Backplanes ........................................................ 45
Dual Mode Serial Management Interface (SMI) ........................................................................................................ 45
13.1 PHY Register Access with SMI in MSA mode .................................................................................... 46
13.1.1
13.1.2
13.1.3
13.1.4
Write Operation - Random Write ..........................................................................................................48
Write Operation - Sequential Write .......................................................................................................49
Read Operation - Random Read .........................................................................................................50
Read Operation - Sequential Read ......................................................................................................51
13.2 PHY Register Access with SMI in IEEE Mode ................................................................................... 52
13.3 SMI Interrupt ....................................................................................................................................... 53
14
15
LED Interface .................................................................................................................................................................. 54
14.1 Serial LED Output ............................................................................................................................... 56
Test Mode Interface (JTAG) ......................................................................................................................................... 57
15.1 Supported Instructions and Instruction Codes .................................................................................... 58
15.2 Boundary-Scan Register Cell Order ................................................................................................... 59
16
17
18
Enhanced ActiPHY Power Management ................................................................................................................... 60
16.1 Operation in Enhanced ActiPHY Mode .............................................................................................. 60
16.2 Low power state ................................................................................................................................. 61
16.3 LP Wake up state ............................................................................................................................... 61
16.4 Normal operating state ....................................................................................................................... 61
Ethernet In-line Powered Device Support ................................................................................................................. 62
17.1 Cisco In-Line Powered Device Detection ........................................................................................... 62
17.2 In-Line Power Ethernet Switch Diagram ............................................................................................. 62
17.3 In-Line Powered Device Detection (Cisco Method) ............................................................................ 62
17.4 IEEE 802.3af (DTE Power via MDI) ................................................................................................... 63
Advanced Test Modes .................................................................................................................................................. 64
18.1 1000BASE-T Ethernet Packet Generator (EPG) ................................................................................ 64
18.2 1000BASE-T CRC Counter ................................................................................................................ 64
18.3 Far-end Loopback .............................................................................................................................. 64
18.4 Near-end Loopback ............................................................................................................................ 64
18.5 Connector Loopback .......................................................................................................................... 65
6 of 165
VMDS-10105 Revision 4.1
October 2006
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