Datasheet > VSC8164QR

VSC8164QR

更新时间： 2024-02-08 05:56:13

品牌	Logo	应用领域
VITESSE		/
页数	文件大小	规格书
16页	156K
描述
2.488 Gbit/sec to 2.7Gbit/sec 1:16 SONET/SDH Demux

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技术参数
数据手册

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VSC8164QR 技术参数

生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	HFQFP,	针数：	128
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.84	应用程序：	SONET;SDH
JESD-30 代码：	R-PQFP-G128	长度：	20 mm
功能数量：	1	端子数量：	128
封装主体材料：	PLASTIC/EPOXY	封装代码：	HFQFP
封装形状：	RECTANGULAR	封装形式：	FLATPACK, HEAT SINK/SLUG, FINE PITCH
认证状态：	Not Qualified	座面最大高度：	2.35 mm
标称供电电压：	3.3 V	表面贴装：	YES
电信集成电路类型：	ATM/SONET/SDH MUX/DEMUX	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	QUAD
宽度：	14 mm	Base Number Matches：	1

VSC8164QR 数据手册

VITESSE

SEMICONDUCTOR CORPORATION

reliminary Datasheet

2.488 Gbit/sec to 2.7Gbit/sec

1:16 SONET/SDH Demux

SC8164

Features

• 2.488Gb/s 1:16 Demultiplexer

• Differential LVPECL Low Speed Interface

• Single +3.3V Supply

• Targeted for SONET OC-48 / SDH STM-16

Applications

• 128 Pin 14x20mm PQFP Package

• Supports FEC rates up to 2.7Gb/s

General Description

The VSC8164 is a 1:16 demultiplexer for use in SONET/SDH systems operating at a standard 2.488Gb/s

data rate or forward error correction (FEC) data rate up to 2.7Gb/s. The device operates using a single 3.3V

power supply, and is packaged in a thermally enhanced plastic package. The thermal performance of the

128PQFP allows the use of the VSC8164 without a heat sink under most thermal conditions.

VSC8164 Block DIagram

D0+

D0-

DI+

DI-

HSCLKI+

HSCLKI-

D15+

D15-

Divide by

CLK16O+

CLK16O-

CLK32O+

CLK32O-

Divide by

Functional Description

Low Speed Interface

The demultiplexed serial stream is made available by a 16 bit differential LVPECL interface D[15:0] with

accompanying differential LVPECL divide by 16 clock CLK16O± and divide by 32 clock CLK32O±. The low

speed LVPECL output drivers are designed to drive a 50Ω transmission line. The transmission line can be DC

terminated with a split end termination scheme (see Figure 1), or DC terminated by 50Ω to V -2V on each line

(see Figure 2). At any time, the equivalent split-end termination technique can be substituted for the traditional

50Ω to V -2V on each line. AC coupling can be achieved by a number of methods. Figure 3 illustrates an AC

coupling method for the occasion when the downstream device provides the bias point for AC coupling. If the

downstream device were to have internal termination, the line to line 100Ω resistor may not be necessary. The

divide by 32 output can be used to provide a reference clock for the clock multiplication unit on the VSC8163.

G52239-0, Rev. 3.3

5/17/00

VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

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