Datasheet > 电信电路 > ATM/SONET/SDH 集成电路> VSC8117QP2

VSC8117QP2

更新时间： 2024-01-16 10:08:41

品牌	Logo	应用领域
VITESSE		时钟发生器 ATM集成电路 SONET集成电路 SDH集成电路电信集成电路电信电路异步传输模式
页数	文件大小	规格书
22页	408K
描述
ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery

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VSC8117QP2 技术参数

生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	FQFP,	针数：	64
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.82	Is Samacsys：	N
应用程序：	ATM;SDH;SONET	JESD-30 代码：	S-PQFP-G64
长度：	10 mm	功能数量：	1
端子数量：	64	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	FQFP	封装形状：	SQUARE
封装形式：	FLATPACK, FINE PITCH	认证状态：	Not Qualified
座面最大高度：	2.45 mm	标称供电电压：	3.3 V
表面贴装：	YES	电信集成电路类型：	ATM/SONET/SDH TRANSCEIVER
温度等级：	INDUSTRIAL	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	QUAD
宽度：	10 mm	Base Number Matches：	1

VSC8117QP2 数据手册

VITESSE

SEMICONDUCTOR CORPORATION

Data Sheet

ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux

with Integrated Clock Generation and Clock Recovery

VSC8117

Good analog design practices should be applied to the board design for these external components. Tightly

controlled analog ground and power planes should be provided for the PLL portion of the circuitry. The dedi-

cated PLL power (VDDA) and ground (VSSA) pins should have quiet supply planes to minimize jitter genera-

tion within the clock synthesis unit. This is accomplished by either using a ferrite bead or a C-L-C choke (π

filter) on the (VDDA) power pins. Note: Vitesse recommends a (π filter) C-L-C choke over using a ferrite bead.

All ground planes should be tied together using multiple vias.

Reference Clocks

To improve jitter performance and to provide flexibility, an additional differential PECL reference clock

input is provided. This reference clock is internally XNOR’d with a TTL reference clock input to generate the

reference for the CMU. Vitesse recommends using the differential PECL input and tieing the unused TTL refer-

ence clock low. If the TTL reference clock is used the positive side of the differential PECL reference clock

“REFCLKP+” should be tied to ground. “REFCLKP+/-” are internally biased with on-chip resistors to 1.65(for

3.3V case) volts, see figure 13 for schematic of internal biasing of differential I/O’s.

The CRU has the option of either using the CMU’s reference clock or its own independent reference clock

“CRUREFCLK”. This is accomplished with the control signal “CRUREFSEL”. The “CRUREFCLK” should be

used if the system is being operated in either a regeneration or looptiming mode. In either of these modes the

quality of the “CRUREFCLK” is not a concern, thus it can be driven by a simple 77.76MHz crystal, the key is

its’ independent of the CMU’s reference clock.

Table 1: Recommended External Capacitor Values

Reference

Frequency

[MHz]

Divide Ratio

Type

Size

Tol.

19.44

77.76

0.1

X7R

0603/0805

+/-10%

Figure 6: External Integrator Capacitor

CP = 0.1 µF

CP2

CP1

CN1

CN2

CN = 0.1 µF

G52221-0, Rev. 4.1

1/8/00

VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

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VSC8122-FECQP	VITESSE	Clock Recovery Circuit, 1-Func, PQFP64, 10 X 10 MM, HEAT SPREADER, PLASTIC, QFP-64	获取价格

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