Datasheet > VSC8113QB-03

VSC8113QB-03

更新时间： 2024-02-16 07:04:48

品牌	Logo	应用领域
VITESSE		ATM 异步传输模式电信电信集成电路
页数	文件大小	规格书
22页	224K
描述
Transceiver, 1-Func, PQFP100, 14 X 20 MM, 2.70 MM HEIGHT, PLASTIC, QFP-100

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技术参数
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VSC8113QB-03 技术参数

生命周期：	Transferred	零件包装代码：	QFP
包装说明：	HQFP,	针数：	100
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.82	JESD-30 代码：	R-PQFP-G100
长度：	20 mm	功能数量：	1
端子数量：	100	封装主体材料：	PLASTIC/EPOXY
封装代码：	HQFP	封装形状：	RECTANGULAR
封装形式：	FLATPACK, HEAT SINK/SLUG	认证状态：	Not Qualified
座面最大高度：	3.4 mm	标称供电电压：	3.3 V
表面贴装：	YES	电信集成电路类型：	ATM/SONET/SDH TRANSCEIVER
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	QUAD	宽度：	14 mm
Base Number Matches：	1

VSC8113QB-03 数据手册

VSC8113

Data Sheet

Facility Loopback

The Facility Loopback function is controlled by the FACLOOP signal. When the FACLOOP signal is set HIGH, the

Facility Loopback mode is activated and the high-speed serial receive data (RXDATAIN) is presented at the high-

speed transmit output (TXDATAOUT). See Figure 3. In addition, the high-speed received/recovered clock is selected

and presented at the high-speed transmit clock output (TXCLKOUT). In Facility Loopback mode the high-speed

receive data (RXDATAIN) is also converted to parallel data and presented at the low-speed receive data output pins

(RXOUT[7:0]). The receive clock (RXCLKIN) is also divided down and presented at the low-speed clock output

(RXLSCKOUT).

1:8

RXOUT[7:0]

TXIN[7:0]

CRU

RXDATAIN

Serial to

Parallel

Recovered

Clock

RXCLKIN

8:1

Parallel to

Serial

TXDATAOUT

TXCLKOUT

FACLOOP

PLL

Figure 3. Facility Loopback Data Path

Equipment Loopback

The Equipment Loopback function is controlled by the EQULOOP signal. When the EQULOOP signal is set HIGH,

the Equipment Loopback mode is activated and the high-speed transmit data generated from the parallel-to-serial

conversion of the low-speed data (TXIN[7:0]) is selected and converted back to parallel data in the receiver section

and presented at the low-speed parallel outputs (RXOUT[7:0]). See Figure 4 on page 6. The internally generated

155MHz/622MHz clock is used to generate the low-speed receive clock output (RXLSCKOUT). In Equipment

Loopback mode, the transmit data (TXIN[7:0]) is serialized and presented at the high-speed output (TXDATAOUT),

along with the high-speed transmit clock (TXCLKOUT) which is generated by the on-chip clock multiplier unit.

CRU Equipment Loopback

Exactly the same as equipment loopback, the point where the transmit data is looped back is moved all the way back

to the high-speed I/O. When the CRUEQLP signal is set HIGH, transmit data is looped back to the CRU, replacing

RXDATAIN±.

5 of 22

G52154, Rev 4.5

6/28/02

Confidential

1 2 3 456 7 8...22

中文翻译

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与VSC8113QB-03相关器件

型号	品牌	获取价格	描述	数据表
VSC8113QB-04	VITESSE	获取价格	Transceiver, 1-Func, PQFP100, 14 X 20 MM, 2.70 MM HEIGHT, PLASTIC, QFP-100
VSC8113QB1	VITESSE	获取价格	ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Re
VSC8113QB2	VITESSE	获取价格	ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Re
VSC8114	VITESSE	获取价格	ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Re
VSC8114QB	VITESSE	获取价格	ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Re
VSC8114QB1	VITESSE	获取价格	ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Re
VSC8114QB2	VITESSE	获取价格	ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Re
VSC8115	VITESSE	获取价格	STS-12/STS-3 Multi Rate Clock and Data Recovery Unit
VSC8115XYA	MICROSEMI	获取价格	Clock Recovery Circuit, 1-Func, PDSO20, 4.40 X 6.50 MM, LEAD FREE, TSSOP-20
VSC8115XYA-02	MICROSEMI	获取价格	Clock Recovery Circuit, 1-Func, PDSO20, 4.40 X 6.50 MM, LEAD FREE, TSSOP-20

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