Datasheet > VSC8113QB-03

VSC8113QB-03

更新时间： 2024-01-31 09:46:59

品牌	Logo	应用领域
VITESSE		ATM 异步传输模式电信电信集成电路
页数	文件大小	规格书
22页	224K
描述
Transceiver, 1-Func, PQFP100, 14 X 20 MM, 2.70 MM HEIGHT, PLASTIC, QFP-100

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技术参数
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VSC8113QB-03 技术参数

生命周期：	Transferred	零件包装代码：	QFP
包装说明：	HQFP,	针数：	100
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.82	JESD-30 代码：	R-PQFP-G100
长度：	20 mm	功能数量：	1
端子数量：	100	封装主体材料：	PLASTIC/EPOXY
封装代码：	HQFP	封装形状：	RECTANGULAR
封装形式：	FLATPACK, HEAT SINK/SLUG	认证状态：	Not Qualified
座面最大高度：	3.4 mm	标称供电电压：	3.3 V
表面贴装：	YES	电信集成电路类型：	ATM/SONET/SDH TRANSCEIVER
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	QUAD	宽度：	14 mm
Base Number Matches：	1

VSC8113QB-03 数据手册

VSC8113

Data Sheet

FUNCTIONAL DESCRIPTION

The VSC8113 is designed to provide a SONET/SDH-compliant interface between the high-speed optical networks

and the lower speed User Network Interface devices such as the PM5355 S/UNI-622. The VSC8113 converts 8-bit

parallel data at 77.76Mb/s or 19Mb/s to a serial bit stream at 622.08Mb/s or 155.52Mb/s, respectively. The VSC8113

also provides a Facility Loopback function which loops the received high-speed data and clock (optionally recovered

on-chip) directly to the high-speed transmit outputs. A Clock Multiplier Unit (CMU) is integrated into the transmit

circuit to generate the high-speed clock for the serial output data stream from input reference frequencies of 19.44,

38.88, 51.84 or 77.76 MHz. The CMU can be bypassed with the received/recovered clock in loop timing mode thus

synchronizing the entire part to a single clock. See the Block Diagram for major functional blocks associated with the

VSC8113.

The receive section provides the serial-to-parallel conversion, converting the 622Mb/s or 1.55.52Mb/s bit stream to an

8-bit parallel output at 19.44Mb/s or 77.76MHz, respectively. A Clock Recovery Unit (CRU) is integrated into the

receive circuit to recover the high-speed clock from the received serial data stream. The receive section provides an

Equipment Loopback function which will loop the low-speed transmit data and clock back through the receive

section to the 8-bit parallel data bus and clock outputs.The VSC8113 also provides the option of selecting between

either its internal CRU’s recovered clock and data signals or optics containing a CRU clock and data signals. (In this

mode the VSC8113 operates just like the VSC8111). The receive section also contains a SONET/SDH frame detector

circuit which is used to provide frame pluses during the A1, A2 boundary in the serial to parallel converter. This only

occurs when OOF is HIGH. Both internal and external LOS functions are supported.

Transmit Section

Byte-wide data is presented to TXIN[7:0] and is clocked into the part on the rising edge of TXLSCKIN. See Figure 1.

The data is then serialized (MSB leading) and presented at the TXDATAOUT+/- pins. TXDATAOUT is clocked out

on the falling edge of TXCLKOUT+. The serial output stream is synchronized to the CMU generated clock which is

a phase-locked and frequency scaled version of the input reference clock. External control inputs B0-B2 and STS-12

select the multiply ratio of the CMU for either STS-12 (622Mb/s) or STS-3 (155MbS) transmission (see Table 12). A

divide-by-8 version of the CMU clock (TXLSCKOUT) should be used to synchronize the transmit interface of the

UNI device to the transmit input registers on the VSC8113 (see Interconnecting the Byte Clocks section).

VSC8113

PM5355

TXDATAOUT+

TXDATAOUT-

TXIN[7:0]

TXCLKOUT+

TXCLKOUT-

TXLSCKIN

TXLSCKOUT

REFCLK

CMU

Divide-by-8

Figure 1. Data and Clock Transmit Block Diagram

3 of 22

G52154, Rev 4.5

6/28/02

Confidential

1 234 5 6 7...22

中文翻译

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与VSC8113QB-03相关器件

型号	品牌	获取价格	描述	数据表
VSC8113QB-04	VITESSE	获取价格	Transceiver, 1-Func, PQFP100, 14 X 20 MM, 2.70 MM HEIGHT, PLASTIC, QFP-100
VSC8113QB1	VITESSE	获取价格	ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Re
VSC8113QB2	VITESSE	获取价格	ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Re
VSC8114	VITESSE	获取价格	ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Re
VSC8114QB	VITESSE	获取价格	ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Re
VSC8114QB1	VITESSE	获取价格	ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Re
VSC8114QB2	VITESSE	获取价格	ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Re
VSC8115	VITESSE	获取价格	STS-12/STS-3 Multi Rate Clock and Data Recovery Unit
VSC8115XYA	MICROSEMI	获取价格	Clock Recovery Circuit, 1-Func, PDSO20, 4.40 X 6.50 MM, LEAD FREE, TSSOP-20
VSC8115XYA-02	MICROSEMI	获取价格	Clock Recovery Circuit, 1-Func, PDSO20, 4.40 X 6.50 MM, LEAD FREE, TSSOP-20

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