Datasheet > VSC8113QB-03

VSC8113QB-03

更新时间： 2024-02-15 05:50:22

品牌	Logo	应用领域
VITESSE		ATM 异步传输模式电信电信集成电路
页数	文件大小	规格书
22页	224K
描述
Transceiver, 1-Func, PQFP100, 14 X 20 MM, 2.70 MM HEIGHT, PLASTIC, QFP-100

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技术参数
数据手册

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VSC8113QB-03 技术参数

生命周期：	Transferred	零件包装代码：	QFP
包装说明：	HQFP,	针数：	100
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.82	JESD-30 代码：	R-PQFP-G100
长度：	20 mm	功能数量：	1
端子数量：	100	封装主体材料：	PLASTIC/EPOXY
封装代码：	HQFP	封装形状：	RECTANGULAR
封装形式：	FLATPACK, HEAT SINK/SLUG	认证状态：	Not Qualified
座面最大高度：	3.4 mm	标称供电电压：	3.3 V
表面贴装：	YES	电信集成电路类型：	ATM/SONET/SDH TRANSCEIVER
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	QUAD	宽度：	14 mm
Base Number Matches：	1

VSC8113QB-03 数据手册

VSC8113

Data Sheet

Receive Section

High-speed Non-Return to Zero (NRZ) serial data at 155Mb/s or 622Mb/s are received by the RXDATAIN inputs.

The CRU recovers the high-speed clock from the serial data input. The serial data is converted to byte-wide parallel

data and presented on RXOUT[7:0] pins. A divide-by-8 version of the high-speed clock (RXLSCKOUT) should be

used to synchronize the byte-serial RXOUT[7:0] data with the receive portion of the UNI device. The on-chip CRU is

bypassed by setting the DSBLCRU input HIGH. In this mode, the serial input data and corresponding clock are

received by the RXDATAIN and RXCLKIN inputs, respectively. RXDATAIN is clocked in on the rising edge of

RXCLKIN+. See Figure 2.

The receive section also includes frame detection and recovery circuitry which detects the SONET/SDH frame, aligns

the received serial data on byte boundaries, and initiates a frame pulse on FP coincident with the byte-aligned data.

The frame recovery is initiated when OOF is held HIGH which must occur at least 4 byte clock cycles before the

A1A2 boundary. The OOF input control is a level-sensitive signal, and the VSC8113 will continually perform frame

detection and recovery as long as this pin is held HIGH even if one or more frames has been detected. Frame

detection and recovery occurs when a series of three A1 bytes followed by three A2 bytes has been detected. The

parallel output data on RXOUT[7:0] will be byte-aligned starting on the third A2 byte. When a frame is detected, a

single byte clock period long pulse is generated on FP which is synchronized with the byte-aligned third A2 byte on

RXOUT[7:0]. The frame detector sends a FP pulse only if OOF is HIGH.

Loss of Signal

The VSC8113 features Loss of Signal (LOS) detection. LOS is declared if the incoming serial data stream has no

transition continuously for more than 128 bits. During an LOS condition, the VSC8113 forces the receive data LOW

which is an indication for any downstream equipment that an optical interface failure has occurred. The receive

section continues to be clocked by the CRU as it is now locked to the CRUREFCLK unless DSBLCRU is active, in

which case it will be clocked by the CMU. This LOS condition will be removed when the part detects more than 16

transitions in a 128-bit time window. This LOS detection feature can be disabled by applying a high level to

LOSDETEN_ input. The VSC8113 also has a TTL input (LOSTTL) and a PECL input (LOSPECL) to force the part

into a LOS state. Most optics have a PECL output usually called “SD” or “FLAG” indicating a lack of or presence of

optical power. Depending on the optics manufactured, this signal is either active HIGH or active LOW. The LOSTTL

and LOSPECL inputs are XNOR’d to generate an internal LOS control signal (see Figure 2). The optics “SD” output

should be connected to LOSPECL. The LOSTTL input should be tied LOW if the optics “SD” output is active HIGH.

If active LOW, tie LOSTTL HIGH. The inverse is true if the optics use “FLAG” for loss of signal.

VSC8113

PM5355

RXOUT[7:0]

LOSPECL

LOSTTL

LOSDETEN_

DSBLCRU

RXDATAIN+/-

CRU

RXLSCKOUT

Divide-by-8

CRULOCKDET

RXCLKIN+/-

CMU

Figure 2. Data and Clock Receive Block Diagram

4 of 22

G52154, Rev 4.5

6/28/02

Confidential

1 2 345 6 7...22

中文翻译

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与VSC8113QB-03相关器件

型号	品牌	获取价格	描述	数据表
VSC8113QB-04	VITESSE	获取价格	Transceiver, 1-Func, PQFP100, 14 X 20 MM, 2.70 MM HEIGHT, PLASTIC, QFP-100
VSC8113QB1	VITESSE	获取价格	ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Re
VSC8113QB2	VITESSE	获取价格	ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Re
VSC8114	VITESSE	获取价格	ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Re
VSC8114QB	VITESSE	获取价格	ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Re
VSC8114QB1	VITESSE	获取价格	ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Re
VSC8114QB2	VITESSE	获取价格	ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Re
VSC8115	VITESSE	获取价格	STS-12/STS-3 Multi Rate Clock and Data Recovery Unit
VSC8115XYA	MICROSEMI	获取价格	Clock Recovery Circuit, 1-Func, PDSO20, 4.40 X 6.50 MM, LEAD FREE, TSSOP-20
VSC8115XYA-02	MICROSEMI	获取价格	Clock Recovery Circuit, 1-Func, PDSO20, 4.40 X 6.50 MM, LEAD FREE, TSSOP-20

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