Datasheet > VSC8113QB-03

VSC8113QB-03

更新时间： 2024-01-30 07:34:22

品牌	Logo	应用领域
VITESSE		ATM 异步传输模式电信电信集成电路
页数	文件大小	规格书
22页	224K
描述
Transceiver, 1-Func, PQFP100, 14 X 20 MM, 2.70 MM HEIGHT, PLASTIC, QFP-100

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VSC8113QB-03 技术参数

生命周期：	Transferred	零件包装代码：	QFP
包装说明：	HQFP,	针数：	100
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.82	JESD-30 代码：	R-PQFP-G100
长度：	20 mm	功能数量：	1
端子数量：	100	封装主体材料：	PLASTIC/EPOXY
封装代码：	HQFP	封装形状：	RECTANGULAR
封装形式：	FLATPACK, HEAT SINK/SLUG	认证状态：	Not Qualified
座面最大高度：	3.4 mm	标称供电电压：	3.3 V
表面贴装：	YES	电信集成电路类型：	ATM/SONET/SDH TRANSCEIVER
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	QUAD	宽度：	14 mm
Base Number Matches：	1

VSC8113QB-03 数据手册

VSC8113

Data Sheet

Clock Synthesis

The VSC8113 uses an integrated Phase-Locked Loop (PLL) for clock synthesis of the 622MHz high-speed clock

used for serialization in the transmitter section. The PLL is comprised of a Phase-Frequency Detector (PFD), an

integrating operation amplifier and a Voltage Controlled Oscillator (VCO) configured in classic feedback system. The

PFD compares the selected divided-down version of the 622MHz VCO (for pins B0-B2, select divide-by ratios of 8,

12, 16 and 32, see Table 13 on page 13) and the reference clock. The integrator provides a transfer function between

input phase error and output voltage control. The VCO portion of the PLL is a voltage-controlled ring-oscillator with

a center frequency of 622MHz.

The reactive elements of the integrator are located off-chip and are connected to the feedback loop of the amplifier

through the CP1, CP2, CN1 and CN2 pins. The configuration of these external surface-mounted capacitors is shown

in Figure 6 on page 7. Table 1 on page 7 shows the recommended external capacitor values for the configurable

reference frequencies.

Good analog design practices should be applied to the board design for these external components. Tightly controlled

analog ground and power planes should be provided for the PLL portion of the circuitry. The dedicated PLL power

(VDDA) and ground (VSSA) pins should have quiet supply planes to minimize jitter generation within the clock

synthesis unit. This is accomplished by either using a ferrite bead or a C-L-C choke (π filter) on the (VDDA) power

pins. Note: Vitesse recommends a (π filter) C-L-C choke over using a ferrite bead. All ground planes should be tied

together using multiple vias.

The VSC8113 features a Lock Detect function for the CMU, CMULOCKDET. It generates low-going pulses when

the CMU is locked to the incoming REFCLK. This is accomplished by comparing the phase of the synthesized clock

to the reference clock. If the CMULOCKDET output remains HIGH for >10µs, the CMU is locked.

Table 1: Recommended External Capacitor Values

Reference Frequency [MHz]

Divide Ratio

0.1

Type

X7R

Size

Tolerance

±10%

19.44

38.88

51.84

77.76

0603/0803

±10%

CP = 0.1µF

CP1

CP2

CN1

CN2

CN = 0.1µF

Figure 6. External Integrator Capacitor

Reference Clocks

To improve jitter performance and to provide flexibility, an additional differential PECL reference clock input is

provided. This reference clock is internally XNOR’d with a TTL reference clock input to generate the reference for

the CMU. Vitesse recommends using the differential PECL input and tying the unused TTL reference clock LOW. If

7 of 22

G52154, Rev 4.5

6/28/02

Confidential

1...4 5 678 9 10...22

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与VSC8113QB-03相关器件

型号	品牌	获取价格	描述	数据表
VSC8113QB-04	VITESSE	获取价格	Transceiver, 1-Func, PQFP100, 14 X 20 MM, 2.70 MM HEIGHT, PLASTIC, QFP-100
VSC8113QB1	VITESSE	获取价格	ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Re
VSC8113QB2	VITESSE	获取价格	ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Re
VSC8114	VITESSE	获取价格	ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Re
VSC8114QB	VITESSE	获取价格	ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Re
VSC8114QB1	VITESSE	获取价格	ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Re
VSC8114QB2	VITESSE	获取价格	ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Re
VSC8115	VITESSE	获取价格	STS-12/STS-3 Multi Rate Clock and Data Recovery Unit
VSC8115XYA	MICROSEMI	获取价格	Clock Recovery Circuit, 1-Func, PDSO20, 4.40 X 6.50 MM, LEAD FREE, TSSOP-20
VSC8115XYA-02	MICROSEMI	获取价格	Clock Recovery Circuit, 1-Func, PDSO20, 4.40 X 6.50 MM, LEAD FREE, TSSOP-20

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