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VSC7959YD-1

更新时间： 2024-01-25 16:56:09
品牌 Logo 应用领域
VITESSE ATM异步传输模式电信光电二极管电信集成电路
页数 文件大小 规格书
14页 148K
描述
Support Circuit, 1-Func, Bipolar, PDSO16, TSSOP-16

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VSC7959YD-1 技术参数

生命周期：Obsolete包装说明：TSSOP, TSSOP16,.25
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.46JESD-30 代码：R-PDSO-G16
长度：5 mm功能数量：1
端子数量：16最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP16,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
电源：3.3/5 V认证状态：Not Qualified
座面最大高度：1.2 mm子类别：ATM/SONET/SDH ICs
标称供电电压：3.3 V表面贴装：YES
技术：BIPOLAR电信集成电路类型：ATM/SONET/SDH SUPPORT CIRCUIT
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
宽度：4.4 mmBase Number Matches：1

VSC7959YD-1 数据手册

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VSC7959  
Data Sheet  
FUNCTIONAL DESCRIPTION  
The VSC7959 is a high-speed limiting amplifier with LOS detect. The VSC7959 is designed to operate with a +3.3V  
or +5V supply in SONET/SDH and Fibre Channel applications up to 3.125Gb/s. The VSC7959 has CML outputs.  
Key features of the VSC7959 are LOS detect, output offset correction, output squelch, low power supply current, and  
fast rise/fall times.  
The inputs of the VSC7959 provide 100Ω input impedance between IN+ and IN– and are intended to be AC-coupled.  
The CML output circuits are designed to tolerate output impedance mismatches and may be AC- or DC-coupled.  
LOS Detect  
LOS Detect utilizes an RMS power detector with programmable LOS indicator to provide two outputs, LOS and  
LOS. The input, TH, is used to set the threshold at which the LOS detector outputs (LOS and LOS) change state. See  
Table 3, "Loss of Signal Specifications" on page 3 for setting the resistor value between TH and ground. Table 4,  
"Loss of Signal Truth Table" on page 3 clarifies the interaction of LOS and SQUELCH.  
Optional Squelch  
Squelch is disabled when SQUELCH is not connected or is set to TTL low level. When SQUELCH is set to TTL high  
level and LOS is asserted, the data outputs, OUT+ and OUT– are forced to static levels. If LOS is not asserted, the  
outputs will not be squelched.  
Offset Correction  
The offset correction feature is provided to ensure that the offsets in the limiting amplifier coupled with its gain do not  
cause the output buffer to give a false output. Because of the high gain of the amplifier, offset correction using a low-  
frequency feedback loop reduces input offset. If no component is placed between pins CZ1 and CZ2, the low  
frequency cut-off is 200kHz. If a 0.1µF capacitor is placed between CZ1 and CZ2, the low frequency cut-off is  
lowered to approximately 2kHz. For Fibre Channel and Gigabit Ethernet applications, leave pins CZ1 and CZ2 open.  
For ATM/SONET and other scrambled non-return-to-zero (NRZ) applications, place a 0.1µF capacitor between CZ1  
and CZ2. This maintains a one-decade separation between the lowest input frequency and the low frequency cut-off.  
The low frequency cut-off of the offset correction loop is given by the following equation:  
fOC = 43 / [2π * 35k (CZ + 100pF)]  
= 196 • 10-6 / (CZ + 100pF)  
= 196 • 10-6 / (0.1µF + 100pF)  
= 1.96kHz  
(EQ 1)  
4 of 14  
G52358, Rev 4.0  
2/10/03  
1234567...14

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