Datasheet > VP0109

VP0109

更新时间： 2023-12-06 20:10:38

品牌	Logo	应用领域
美国微芯 - MICROCHIP		/
页数	文件大小	规格书
5页	640K
描述
This enhancement-mode (normally-off) transistor utilizes a vertical DMOS structure and well-prove

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VP0109 数据手册

Supertex inc.

VP0109

P-Channel Enhancement-Mode

Vertical DMOS FETs

Features

General Description

► Free from secondary breakdown

► Low power drive requirement

► Ease of paralleling

This enhancement-mode (normally-off) transistor utilizes

a vertical DMOS structure and Supertex’s well-proven,

silicon-gate manufacturing process. This combination

produces a device with the power handling capabilities

of bipolar transistors and the high input impedance and

positive temperature coefﬁcient inherent in MOS devices.

Characteristic of all MOS structures, this device is free

from thermal runaway and thermally-induced secondary

breakdown.

► Low C_ISSand fast switching speeds

► Excellent thermal stability

► Integral source-drain diode

► High input impedance and high gain

Applications

► Motor controls

► Converters

Supertex’s vertical DMOS FETs are ideally suited to a

wide range of switching and amplifying applications where

very low threshold voltage, high breakdown voltage, high

input impedance, low input capacitance, and fast switching

speeds are desired.

► Ampliﬁers

► Switches

► Power supply circuits

► Drivers (relays, hammers, solenoids, lamps, memories,

displays, bipolar transistors, etc.)

Ordering Information

Product Summary

Part Number

Package Option

Packing

R_DS(ON)

I_D(ON)

BV_DSS/BV_DGS

(max)

(min)

VP0109N3-G

TO-92

1000/Bag

VP0109N3-G P002

VP0109N3-G P003

VP0109N3-G P005

VP0109N3-G P013

VP0109N3-G P014

-90V

8.0Ω

-500mA

TO-92

2000/Reel

Pin Conﬁguration

-G denotes a lead (Pb)-free / RoHS compliant package.

Contact factory for Wafer / Die availablity.

Devices in Wafer / Die form are lead (Pb)-free / RoHS compliant.

DRAIN

SOURCE

Absolute Maximum Ratings

Parameter

Value

GATE

Drain-to-source voltage

Drain-to-gate voltage

BV_DSS

BV_DGS

±20V

TO-92

Gate-to-source voltage

Product Marking

Operating and storage temperature

-55^OC to +150^OC

SiVP

0 1 0 9

YYWW

YY = Year Sealed

Absolute Maximum Ratings are those values beyond which damage to the device may

occur. Functional operation under these conditions is not implied. Continuous operation

of the device at the absolute rating level may affect device reliability. All voltages are

referenced to device ground.

WW = Week Sealed

= “Green” Packaging

Package may or may not include the following marks: Si or

Typical Thermal Resistance

TO-92

Package

θ_ja

TO-92

132^OC/W

Doc.# DSFP-VP0109

C082313

Supertex inc.

www.supertex.com

12 3 4 5

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