List of figures
VND7050AJ12
List of figures
Figure 1: Block diagram..............................................................................................................................5
Figure 2: Configuration diagram (top view).................................................................................................6
Figure 3: Current and voltage conventions.................................................................................................7
Figure 4: IOUT/ISENSE versus IOUT.......................................................................................................14
Figure 5: Current sense accuracy versus IOUT .......................................................................................15
Figure 6: Switching times and Pulse skew ...............................................................................................15
Figure 7: CurrentSense timings................................................................................................................16
Figure 8: TDSTKON..................................................................................................................................16
Figure 9: Standby mode activation ...........................................................................................................18
Figure 10: Standby state diagram.............................................................................................................18
Figure 11: OFF-state output current .........................................................................................................19
Figure 12: Standby current .......................................................................................................................19
Figure 13: IGND(ON) vs. Tcase ...............................................................................................................19
Figure 14: Logic Input high level voltage ..................................................................................................19
Figure 15: Logic Input low level voltage....................................................................................................19
Figure 16: High level logic input current ...................................................................................................19
Figure 17: Low level logic input current ....................................................................................................20
Figure 18: Logic Input hysteresis voltage .................................................................................................20
Figure 19: Undervoltage shutdown...........................................................................................................20
Figure 20: On-state resistance vs. Tcase.................................................................................................20
Figure 21: On-state resistance vs. Vcc.....................................................................................................20
Figure 22: Turn-on voltage slope..............................................................................................................20
Figure 23: Turn-off voltage slope..............................................................................................................21
Figure 24: Won vs Tcase..........................................................................................................................21
Figure 25: Woff vs Tcase..........................................................................................................................21
Figure 26: ILIMH vs. Tcase.......................................................................................................................21
Figure 27: OFF-state open-load voltage detection threshold ...................................................................21
Figure 28: Vsense clamp vs Tcase...........................................................................................................21
Figure 29: Vsenseh vs Tcase ...................................................................................................................22
Figure 30: Application diagram.................................................................................................................24
Figure 31: Simplified internal structure - GND network protection with Schottly diode............................24
Figure 32: Simplified internal structure - GND network protection with MOSFET....................................25
Figure 33: Cranking profile .......................................................................................................................27
Figure 34: CurrentSense and diagnostic – block diagram........................................................................28
Figure 35: CurrentSense block diagram...................................................................................................29
Figure 36: Analogue HSD – open-load detection in off-state ...................................................................30
Figure 37: Open-load / short to VCC condition.........................................................................................31
Figure 38: Maximum turn off current versus inductance ..........................................................................33
Figure 39: PowerSSO-12 on two-layers PCB (2s0p to JEDEC JESD 51-5)............................................34
Figure 40: PowerSSO-12 on four-layers PCB (2s2p to JEDEC JESD 51-7) ...........................................34
Figure 41: Rthj-amb vs PCB copper area in open box free air condition (one channel on).....................35
Figure 42: PowerSSO-12 thermal impedance junction ambient single pulse (one channel on) ..............35
Figure 43: Thermal fitting model of a double-channel HSD in PowerSSO-12..........................................36
Figure 44: PowerSSO-12 package dimensions........................................................................................37
Figure 45: PowerSSO-12 reel 13" ............................................................................................................38
Figure 46: PowerSSO-12 carrier tape ......................................................................................................39
Figure 47: PowerSSO-12 schematic drawing of leader and trailer tape ..................................................40
Figure 48: PowerSSO-12 marking information.........................................................................................40
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