List of figures
VND7030AJ
List of figures
Figure 1: Block diagram..............................................................................................................................5
Figure 2: Configuration diagram (top view).................................................................................................6
Figure 3: Current and voltage conventions.................................................................................................7
Figure 4: IOUT/ISENSE versus IOUT.......................................................................................................16
Figure 5: Current sense accuracy versus IOUT .......................................................................................16
Figure 6: Switching time and Pulse skew .................................................................................................17
Figure 7: MultiSense timings (current sense mode).................................................................................17
Figure 8: Multisense timings (chip temperature and VCC sense mode)..................................................18
Figure 9: TDSTKON..................................................................................................................................18
Figure 10: Latch functionality - behavior in hard short circuit condition (TAMB << TTSD) ......................20
Figure 11: Latch functionality - behavior in hard short circuit condition....................................................20
Figure 12: Latch functionality - behavior in hard short circuit condition (autorestart mode + latch off)....21
Figure 13: Standby mode activation .........................................................................................................21
Figure 14: Standby state diagram.............................................................................................................22
Figure 15: OFF-state output current .........................................................................................................22
Figure 16: Standby current .......................................................................................................................22
Figure 17: IGND(ON) vs. Iout ...................................................................................................................23
Figure 18: Logic Input high level voltage ..................................................................................................23
Figure 19: Logic Input low level voltage....................................................................................................23
Figure 20: High level logic input current ...................................................................................................23
Figure 21: Low level logic input current ....................................................................................................23
Figure 22: Logic Input hysteresis voltage .................................................................................................23
Figure 23: FaultRST Input clamp voltage .................................................................................................24
Figure 24: Undervoltage shutdown...........................................................................................................24
Figure 25: On-state resistance vs. Tcase.................................................................................................24
Figure 26: On-state resistance vs. VCC ...................................................................................................24
Figure 27: Turn-on voltage slope..............................................................................................................24
Figure 28: Turn-off voltage slope..............................................................................................................24
Figure 29: Won vs. Tcase.........................................................................................................................25
Figure 30: Woff vs. Tcase.........................................................................................................................25
Figure 31: ILIMH vs. Tcase.......................................................................................................................25
Figure 32: OFF-state open-load voltage detection threshold ...................................................................25
Figure 33: Vsense clamp vs. Tcase..........................................................................................................25
Figure 34: Vsenseh vs. Tcase ..................................................................................................................25
Figure 35: Application diagram.................................................................................................................27
Figure 36: Simplified internal structure .....................................................................................................27
Figure 37: MultiSense and diagnostic – block diagram............................................................................29
Figure 38: MultiSense block diagram .......................................................................................................30
Figure 39: Analogue HSD – open-load detection in off-state ...................................................................31
Figure 40: Open-load / short to VCC condition.........................................................................................32
Figure 41: GND voltage shift ....................................................................................................................33
Figure 42: Maximum turn off current versus inductance ..........................................................................35
Figure 43: PowerSSO-16 on two-layers PCB (2s0p to JEDEC JESD 51-5)............................................36
Figure 44: PowerSSO-16 on four-layers PCB (2s2p to JEDEC JESD 51-7) ...........................................36
Figure 45: Rthj-amb vs PCB copper area in open box free air condition (one channel on).....................37
Figure 46: PowerSSO-16 thermal impedance junction ambient single pulse (one channel on) ..............37
Figure 47: Thermal fitting model of a double-channel HSD in PowerSSO-16..........................................38
Figure 48: PowerSSO-16 package dimensions........................................................................................39
Figure 49: PowerSSO-16 reel 13" ............................................................................................................41
Figure 50: PowerSSO-16 carrier tape ......................................................................................................42
Figure 51: PowerSSO-16 schematic drawing of leader and trailer tape ..................................................42
Figure 52: PowerSSO-16 marking information.........................................................................................43
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