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VFSD1-S24-S5-SIP PDF预览

VFSD1-S24-S5-SIP

更新时间: 2024-11-14 03:20:11
品牌 Logo 应用领域
CUI /
页数 文件大小 规格书
3页 317K
描述
Dc-Dc Converter

VFSD1-S24-S5-SIP 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete包装说明:SIP-7/4
Reach Compliance Code:unknown风险等级:5.74
模拟集成电路 - 其他类型:DC-DC UNREGULATED POWER SUPPLY MODULE最大输入电压:26.4 V
最小输入电压:21.6 V标称输入电压:24 V
JESD-30 代码:R-PSMA-P4长度:19.5 mm
最大负载调整率:15%功能数量:1
输出次数:1端子数量:4
最高工作温度:85 °C最低工作温度:-40 °C
标称输出电压:5 V封装主体材料:PLASTIC/EPOXY
封装形状:RECTANGULAR封装形式:MICROELECTRONIC ASSEMBLY
峰值回流温度(摄氏度):NOT SPECIFIED表面贴装:NO
技术:HYBRID温度等级:INDUSTRIAL
端子形式:PIN/PEG端子节距:2.54 mm
端子位置:SINGLE处于峰值回流温度下的最长时间:NOT SPECIFIED
最大总功率输出:1 W微调/可调输出:NO
宽度:6 mmBase Number Matches:1

VFSD1-S24-S5-SIP 数据手册

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VFSD1-SIP Series Dc-Dc Converter  
Rev. 12-2005  
Description  
Features  
Designed to convert fixed volt-  
ages into an isolated voltage, the  
VFSD1-SIP series is well suited for  
providing board-mount local sup-  
plies in a wide range of applica-  
tions, including mixed analog/digi-  
tal circuits, test & measurement  
equip., process/machine controls,  
datacom/telecom fields, etc...  
·Isolated 1 W output  
·Temperature range: -40°C~+85°C  
·Unregulated  
·High efficiency to 80%  
·Single voltage output  
·Small footprint  
·SIP package style  
·Industry standard pinout  
·UL94-V0 package  
·No heatsink required  
·3K Vdc isolation  
The semi-regulated output can be  
followed by 3-terminal regulators  
to provide output protection, in  
addition to output regulation.  
·Power density 0.85 W/cm³  
·No external component required  
·Low cost  
Model  
Input Voltage  
Output  
Voltage  
3.3 Vdc  
5 Vdc  
Output Current  
Package  
Number  
Nominal  
3.3 Vdc  
3.3 Vdc  
5 Vdc  
Range  
Max.  
300 mA  
200 mA  
300 mA  
200 mA  
111 mA  
83 mA  
67 mA  
42 mA  
300 mA  
200 mA  
111 mA  
83 mA  
67 mA  
42 mA  
300 mA  
200 mA  
111 mA  
83 mA  
67 mA  
42 mA  
300 mA  
200 mA  
111 mA  
83 mA  
67 mA  
42 mA  
Min.  
30 mA  
20 mA  
30 mA  
20 mA  
12 mA  
9 mA  
Efficiency Style  
UL60950  
VFSD1-S3.3-S3.3-SIP  
VFSD1-S3.3-S5-SIP  
VFSD1-S5-S3.3-SIP  
VFSD1-S5-S5-SIP  
VFSD1-S5-S9-SIP  
VFSD1-S5-S12-SIP  
VFSD1-S5-S15-SIP  
VFSD1-S5-S24-SIP  
VFSD1-S12-S3.3-SIP  
VFSD1-S12-S5-SIP  
VFSD1-S12-S9-SIP  
VFSD1-S12-S12-SIP  
VFSD1-S12-S15-SIP  
VFSD1-S12-S24-SIP  
VFSD1-S15-S3.3-SIP  
VFSD1-S15-S5-SIP  
VFSD1-S15-S9-SIP  
VFSD1-S15-S12-SIP  
VFSD1-S15-S15-SIP  
VFSD1-S15-S24-SIP  
VFSD1-S24-S3.3-SIP  
VFSD1-S24-S5-SIP  
VFSD1-S24-S9-SIP  
VFSD1-S24-S12-SIP  
VFSD1-S24-S15-SIP  
VFSD1-S24-S24-SIP  
3.00~3.60 Vdc  
3.00~3.60 Vdc  
4.5~5.5 Vdc  
72%  
73%  
72%  
78%  
78%  
80%  
81%  
78%  
73%  
79%  
79%  
81%  
81%  
79%  
73%  
74%  
75%  
79%  
79%  
79%  
73%  
79%  
80%  
80%  
80%  
80%  
SIP  
SIP  
SIP  
SIP  
SIP  
SIP  
SIP  
SIP  
SIP  
SIP  
SIP  
SIP  
SIP  
SIP  
SIP  
SIP  
SIP  
SIP  
SIP  
SIP  
SIP  
SIP  
SIP  
SIP  
SIP  
SIP  
NO  
NO  
3.3 Vdc  
5 Vdc  
NO  
5 Vdc  
4.5~5.5 Vdc  
YES  
YES  
YES  
NO  
5 Vdc  
4.5~5.5 Vdc  
9 Vdc  
5 Vdc  
4.5~5.5 Vdc  
12 Vdc  
15 Vdc  
24 Vdc  
3.3 Vdc  
5 Vdc  
5 Vdc  
4.5~5.5 Vdc  
7 mA  
5 Vdc  
4.5~5.5 Vdc  
5 mA  
NO  
12 Vdc  
12 Vdc  
12 Vdc  
12 Vdc  
12 Vdc  
12 Vdc  
15 Vdc  
15 Vdc  
15 Vdc  
15 Vdc  
15 Vdc  
15 Vdc  
24 Vdc  
24 Vdc  
24 Vdc  
24 Vdc  
24 Vdc  
24Vdc  
10.8~13.2 Vdc  
10.8~13.2 Vdc  
10.8~13.2 Vdc  
10.8~13.2 Vdc  
10.8~13.2 Vdc  
10.8~13.2 Vdc  
13.5~16.5 Vdc  
13.5~16.5 Vdc  
13.5~16.5 Vdc  
13.5~16.5 Vdc  
13.5~16.5 Vdc  
13.5~16.5 Vdc  
21.6~26.4 Vdc  
21.6~26.4 Vdc  
21.6~26.4 Vdc  
21.6~26.4 Vdc  
21.6~26.4 Vdc  
21.6~26.4 Vdc  
30 mA  
20 mA  
12 mA  
9 mA  
NO  
YES  
YES  
YES  
YES  
NO  
9 Vdc  
12 Vdc  
15 Vdc  
24 Vdc  
3.3 Vdc  
5 Vdc  
7 mA  
5 mA  
30mA  
20 mA  
12 mA  
9 mA  
NO  
NO  
9 Vdc  
NO  
12 Vdc  
15 Vdc  
24 Vdc  
3.3 Vdc  
5 Vdc  
NO  
7 mA  
NO  
5 mA  
NO  
30 mA  
20 mA  
12 mA  
9 mA  
NO  
YES  
YES  
YES  
YES  
NO  
9 Vdc  
12 Vdc  
15 Vdc  
24 Vdc  
7 mA  
5 mA  
Output Specifications  
Item  
Test conditions  
Min.  
Typ.  
Max.  
1
Units  
Output power  
0.1  
W
Line Regulation  
Load Regulation  
Output voltage accuracy  
Temperature drift  
Output ripple  
For Vin change of 1%, full load  
1.2%  
15%  
10% to 100% full load, nominal line  
See tolerance envelope graph  
@ 100% load  
10%  
0.03  
75  
%/°C  
mVp-p  
Hz  
20 MHz Bandwidth  
50  
Switching frequency  
Full load, nominal input  
100K  
150K  
200K  
V-Infinity, LLC, 20050 SW 112th Ave., Tualatin, OR 97062  
www.v-infinity.com  
1-866-372-1258  

VFSD1-S24-S5-SIP 替代型号

型号 品牌 替代类型 描述 数据表
PEM1-S24-S5-S CUI

完全替代

5 Vdc, 0.2 A, 1 W, 21.6~26.4 Vdc Input Range

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