Performance Specifications
Table 1. Electrical Performance, LVPECL Option
Parameter
Symbol
Min
Typical
Maximum
Units
Supply
Voltage1
VDD
IDD
3.135
2.375
3.3
2.5
3.465
2.625
V
V
Current (No Load)
50
98
mA
Frequency
Nominal Frequency2
Stability2,3 (Ordering Option)
fN
10
350.000
MHz
ppm
20, 25, 50, 100
Outputs
Output Logic Levels4, -10/70°C
Output Logic High
Output Logic Low
VOH
VOL
VDD-1.025
VDD-0.880
VDD-1.620
V
V
V
DD-1.810
Output Logic Levels4, -40/85°C
Output Logic High
Output Logic Low
VOH
VOL
VDD-1.085
VDD-1.830
VDD-0.880
VDD-1.555
V
V
Output Rise and Fall Time4
tR/tF
600
ps
Load
50 ohms into VDD-1.3V
Duty Cycle5
45
50
55
%
Jitter (12 kHz - 20 MHz BW)155.52MHz6
Period Jitter7
RMS
фJ
фJ
0.3
0.7
ps
2.3
20
2.4
0
ps
ps
ps
ps
P/P
Random Jitter
Deterministic Jitter
Enable/Disable
Output Enabled8
Output Disabled
VIH
VIL
0.7*VDD
V
V
0.3*VDD
200
Disable Time
tD
ns
Enable/Disable Leakage Current
200
uA
Enable Pull-Up Resistor
Output Enabled
Output Disabled
33
1
KOhm
MOhm
Start-Up Time
tSU
10
ms
°C
Operating Temp. (Ordering Option)
Package Size
TOP
-10/70 or -40/85
5.0 x 7.0 x 1.8 or 5.08x7.5x2.2
mm
1. The VCC6 power supply pin should be filtered, eg, a 0.1 and 0.01uf capacitor.
2. See Standard Frequencies and Ordering Information for more information.
3. Includes calibration tolerance, operating temperature, supply voltage variations, aging and IR reflow.
4. Figure 1 defines the test circuit and Figure 2 defines these parameters.
5. Duty Cycle is defined as the On/Time Period.
6. Measured using an Agilent E5052, 155.520MHz. Please see “Typical Phase Noise and Jitter Report for the VCC6 series”.
7. Measured using a Wavecrest SIA3300C, 90K samples.
8. Outputs will be Enabled if Enable/Disable is left open.
tR
tF
VDD -1.3V
VOH
1
2
3
6
5
4
50%
VOL
NC
NC
On Time
50 ȍ
Figure 1.
50 ȍ
-1.3V
Period
Figure 2.
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com
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