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V62/04725-01XE

更新时间： 2024-01-21 18:35:30
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德州仪器 - TI 触发器
页数 文件大小 规格书
9页 285K
描述
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET

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V62/04725-01XE 数据手册

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SCAS722 − OCTOBER 2003  
D
Controlled Baseline  
− One Assembly/Test Site, One Fabrication  
Site  
D
D
D
D
4.5-V to 5.5-V V  
Operation  
CC  
Inputs Accept Voltages to 5.5 V  
Max t of 10.5 ns at 5 V  
pd  
Inputs Are TTL-Voltage Compatible  
D
D
Extended Temperature Performance of  
−55°C to 125°C  
Enhanced Diminishing Manufacturing  
Sources (DMS) Support  
D PACKAGE  
(TOP VIEW)  
D
Enhanced Product-Change Notification  
1CLR  
1D  
V
CC  
2CLR  
2D  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
†
D
Qualification Pedigree  
†
Component qualification in accordance with JEDEC and industry  
standards to ensure reliable operation over an extended  
temperature range. This includes, but is not limited to, Highly  
Accelerated Stress Test (HAST) or biased 85/85, temperature  
cycle, autoclave or unbiased HAST, electromigration, bond  
intermetallic life, and mold compound life. Such qualification  
testing should not be viewed as justifying use of this component  
beyond specified performance and environmental limits.  
1CLK  
1PRE  
1Q  
2CLK  
2PRE  
2Q  
1Q  
GND  
2Q  
8
description/ordering information  
The SN74ACT74-EP is a dual positive-edge-triggered D-type flip-flop.  
A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the  
other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup-time  
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs  
at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval,  
data at D can be changed without affecting the levels at the outputs.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
‡
PACKAGE  
T
A
−55°C to 125°C  
SOIC − D  
Tape and reel  
SN74ACT74MDREP  
SACT74MEP  
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
FUNCTION TABLE  
(each flip-flop)  
INPUTS  
OUTPUTS  
CLR  
PRE  
L
CLK  
X
D
X
X
X
H
L
Q
H
L
Q
L
H
L
H
X
H
§
§
H
L
L
X
H
H
H
H
H
↑
H
L
L
H
↑
H
H
L
X
Q
Q
0
0
§
This configuration is nonstable; that is, it does not  
persist when either PRE or CLR returns to its  
inactive (high) level.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
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Copyright 2003, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...9

中文翻译

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V62/04725-01XE 替代型号

型号 品牌 替代类型 描述 数据表
SN74ACT74MDREP TI

完全替代

 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET
MC74ACT74DG ONSEMI

功能相似

 Dual D−Type Positive Edge−Triggered Flip−Flop
SN74ACT74DR TI

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 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

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